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Summary of Contents for Intel IXP28XX
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® Intel IXP28XX Network Processors Hardware Design Guide August 2005 Order Number: 309192-002US Downloaded from Elcodis.com electronic components distributor...
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Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.
3.2.6 IXP28XX Network Processor Power-Up Considerations when using NexMod* Memory Modules ....................37 IXP28XX Network Processor Rambus* Controller Footprint and Via Placement ....38 IXP28XX Network Processor Controller Escape Routing ...........41 IXP28XX Network Processor Three-Channel Controller to HCD NexMod* RDRAM Routing ..........................46 IXP28XX Network Processor Short Channel Routing ............49...
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IXP28XX Network Processor Contents QDR SRAM Interface ......................57 4.4.1 Using x9 Versus x18 QDR SRAM Parts ..............58 4.4.1.1 Examples of the QDR Interface ............. 60 4.4.2 Signal Groups ......................62 4.4.3 QDR Signal Mapping ..................... 62 4.4.4 ClamShell Configuration of SRAMs............... 63 4.4.5...
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IXP28XX Network Processor di/dt Stimulus ................30 Power-up Sequence ........................37 Common VCCR_IO for All Three RACs in the IXP28XX® Network Processor......38 Rambus* Controller Footprint and Via Placement Showing Alternating Dogbone Orientation...39 10 Rambus* Controller Footprint and Via Placement Showing Exploded View of Checkerboard Detail ........................40...
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49 Example Interconnects on the IXP28XX Network Processor, with a Two-QDRII SRAM Load per Channel ..........................86 50 Trace Length from IXP28XX Network Processor to SRAM (C, K, SA, D, and R/W_BW) ..87 51 Trace Length from SRAM to IXP28XX Network Processor (Q Data) ......... 87 52 QDR 0 Routing on Layer 13 - Adjacent QDR Clamshell Pairs ...........
IXP28XX Network Processor Revision History Revision History Date Revision Description August 2005 Updates to Chapter 4 QDR SRAM. December 2004 Initial release Downloaded from Elcodis.com electronic components distributor...
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IXP28XX Network Processor Revision History Downloaded from Elcodis.com electronic components distributor...
Design Considerations or suggestions, based on the development platforms designed by Intel. They should be used as examples, but may not be applicable to particular designs. Note: The guidelines recommended in this document are based on simulation work completed by Intel. This work is ongoing, and recommendations are subject to change.
IXP28XX Network Processor Introduction Table 1. Product Features of IXP28XX Network Processors Feature Description • Operating frequency of up to 1.4 GHz • Configurable to four or eight threads per Microengine • 640 Dwords of local memory per Microengine • Sixteen-entry CAM per Microengine, with single cycle lookup...
0x16 ME Cluster 0 ME Cluster 1 B0564-02 In This Guide This document comprises the following chapters and appendixes that describe the IXP28XX network processor: • Chapter 2, “Power Ratings and Requirements,” describes the minimum and maximum operating voltages and temperatures.
IXP28XX Network Processor Introduction 1.2.1 Typographical Conventions This guide contains the following text and typography conventions: Table 2. Guide Conventions Convention Description Italics New terms and titles of documents or help systems appear in italics. bold Special text for labels of items appears in bold type.
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Phase Lock Loop Packet over SONET Primary PCI, a 64-bit PCI bus operating at 33 or 66 MHz. This bus connects the PPCI ingress and egress IXP28XX network processor to the master and slave PCI-PCI bridge chips. Process/Voltage/Temperature QDR SRAM...
Refer to the following documents or models for more information. All Intel-issued documentation revision numbers are subject to change, and the latest revision should be used. The specific revision numbers referenced should be used for all documents not released by Intel. Contact your field representative for information on obtaining Intel-issued documentation.
IXP28XX Network Processor Power Ratings and Requirements Power Ratings and Requirements ® ® The following sections describe power ratings and requirements for the Intel IXP2800 and Intel IXP2850 Network Processors. Power Ratings Operation beyond the functional operating temperature range (see...
14 W 17.5 W 650 MHz The maximum power parameters represent the worst-case power consumption as measured by running the Intel packet over SONET (POS) reference design processing minimum-size packets (49 bytes) running at full OC-192 line rate. Total power.
IXP28XX Network Processor Power Ratings and Requirements Table 7. Functional Operating Voltage Range – 1.4/1.0 GHz Tolerance Notes Interface Supply Name Description Voltage (V) 1,2,3,4,5 (+/-%) Core power supply 1.3 V Core Core ground VCC_PLL PLL power 1.3 V PLL ground VCC_CLK Ref.
IXP28XX Network Processor Power Ratings and Requirements Table 8. Functional Operating Voltage Range – 650 MHz Tolerance Notes Interface Supply Name Description Voltage (V) 1,2,3,4 (+/-%) Core power supply 1.2 V Core Core ground VCC_PLL PLL power 1.2 V PLL ground VCC_CLK Ref.
IXP28XX Network Processor Power Ratings and Requirements ‘ Table 9. Example Power by Supply – 1.4 GHz Max Power Type Group Names IXP2800 IXP2850 VCCR 1.3 V logic 25.5 W 28.0 W VCCRA VCC_FUSE VCC_PLL VCCA_FC VCCA_SPI4 1.3 V PLL/DLL PAS0_VCCA 1.0 W...
IXP28XX Network Processor Power Ratings and Requirements Table 10. Example Power by Supply – 1.0 GHz Max Power Type Group Names IXP2800 IXP2850 VCCR 1.3 V logic 17.0 W 19.0 W VCCRA VCC_FUSE VCC_PLL VCCA_FC VCCA_SPI4 1.3 V PLL/DLL PAS0_VCCA 1.0 W...
IXP28XX Network Processor Power Ratings and Requirements Table 11. Example Power by Supply – 650 MHz Max Power Type Group Names IXP2800 IXP2850 VCCR 1.2 V logic 10.4 W 11.8 W VCCRA VCC_FUSE VCC_PLL VCCA_FC VCCA_SPI4 1.2 V PLL/DLL PAS0_VCCA 1.0 W...
Power Ratings and Requirements Supply Voltage Power-up Sequence Caution: The IXP28XX network processors each have a prescribed supply voltage bring-up sequence that must be followed, or permanent damage to the device may result. This section provides the bring- up sequence for 1.4 /1.0 GHz devices (Section 2.2.1) and 650 MHz devices...
IXP28XX Network Processor Power Ratings and Requirements 2.2.3 Power Supply Regulation 2.2.3.1 Power-Up Power Supply Regulation During power-up, after NRESET is de-asserted, the device will experience an increase in current consumption after the PLL locks and the system clocks begin to operate at full speed. During this time, a droop on the core power supply may occur due to this increase in current consumption.
IXP28XX Network Processor Power Ratings and Requirements Figure 2. IXDP2800 Decoupling Implementation LC Filter Network Figure 3 shows an example of an LC filter design that can be used to derive the power for the analog and DLL power supplies for the IXP2800 or IXP2850 network processor. For L1, a 10-Ω...
IXP28XX Network Processor Power Ratings and Requirements 2.4.2 Power-up Sequence Figure 5 illustrates the power-up sequence for the IXDP2800 Advanced Development Platform power supply. Figure 5. IXDP2800 Advanced Development Platform Power-up Sequence .75 V 1.0 V 1.2 V 1.4 V 1.35 V...
Power Ratings and Requirements IXP28XX Network Processor Power-On di/dt Profiles Figure 6 illustrates IXP28XX network processor worst case power-up di/dt stimulus. The characteristics of this transient event are as follows: • Reset leakage power is 3.68 W (2.7 A at 1.365 V).
2.5.1 di/dt Droop Analysis Results An exhaustive droop analysis was performed using an Intel system validation platform. The goal of analysis was to correlate the measured power-on di/dt with the theoretical design values. A detailed model of the system board, power delivery circuit and package were developed and simulated using the theoretical di/dt transient events to predict the voltage droop measured at the pins of the device.
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IXP28XX Network Processor Power Ratings and Requirements Hardware Design Guide Downloaded from Elcodis.com electronic components distributor...
0 and 1 populated with channel 2 empty, or channel 0 populated with channels 1 and 2 empty. ® Reads and writes to RDRAM are generated by Microengines, Intel XScale core, and PCI (external Bus Masters and DMA Channels). The controllers also do refresh and calibration cycles to the RDRAMs, transparently to software.
IXP28XX Network Processor RDRAM The multi-tiered NexMod* module contains all of the circuitry for an entire Rambus* channel in a single module. The NexMod* module can be attached either to the main board with pin grid array (PGA) connectors or soldered with ball grid array (BGA) technology. The module incorporates termination resistors, the Direct Rambus* Clock Generator (DRCG), and a Voltage Regulator Module (VRM) on the same modular subsystem as the memory chips.
The following is a list of RSL (Rambus* Signaling Level) trace requirements and recommendations for Rambus* designs: • All signals must be length-matched (RSL and clock signals) from the IXP28XX network processor to each RDRAM pin. Signals are then length-matched for RDRAM to RDRAM pin. •...
3.2.2 Unused Channel Guidelines It is not a requirement to implement all three RDRAM channels available on the IXP28XX network processor. However, if only a single channel is implemented it MUST be channel 0. If two channels are implemented then they MUST be channels 0 and 1. No other channel combinations are supported in these modes.
RDRAM I/O CCR_IO, TERM CMOS supply for the IXP28XX network processor, is common to all three channels as shown in Figure the following requirement must be satisfied by the power delivery design: • The system designer must ensure that V and V never differ by more than 1.6 V.
HCD Module 3 RACs B3431-01 IXP28XX Network Processor Rambus* Controller Footprint and Via Placement The following figures illustrate the IXP28XX network processor Rambus* controller footprint and via placement: • Figure 9, “Rambus* Controller Footprint and Via Placement Showing Alternating Dogbone Orientation”...
IXP28XX Network Processor RDRAM Figure 10 illustrates the IXP28XX network processor Rambus* controller footprint and via placement, showing an exploded view of checkerboard detail. Figure 10. Rambus* Controller Footprint and Via Placement Showing Exploded View of Checkerboard Detail Hardware Design Guide Downloaded from Elcodis.com...
RDRAM IXP28XX Network Processor Three-Channel Controller to HCD NexMod* RDRAM Routing The following figures illustrate routing with the IXP28XX network processor’s three-channel controller to HCD NexMod* RDRAM as implemented on the IXMB2800 development system. • Figure 16, “Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 4”...
IXP28XX Network Processor RDRAM IXP28XX Network Processor Short Channel Routing Figure 20 illustrates an IXP28XX network processor short channel routing example Note: The layout example depicted in Figure 20 was implemented only as a routing study and has not been validated.
IXP28XX Network Processor RDRAM Package Trace Lengths for RDRAM Signals Table 13 provides package trace lengths for RDRAM signals, listed by decreasing lengths in a given logical grouping. The flight time on the package substrate is 154ps/in which differs from the flight delay of standard FR4, typical 180ps/in.
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IXP28XX Network Processor RDRAM Table 13. Package Trace Lengths for RDRAM Signals (Sheet 2 of 2) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) RDR0_RQ[1] 11.432 0.450 RDR1_DQB[6] 8.247...
The coprocessor behaves as a memory-mapped device on the SRAM bus. Introduction This is a design guide for the QDR interface of IXP28XX NPU. It is intended to guide board designers using IXP28XX network processor in their designs employing 4 SRAM loads or less at a clock frequency of 233/250MHz.
IXP28XX Network Processor QDR SRAM significant changes in results or may lead to non-working design altogether. That is why it is strongly recommended that developers thoroughly simulate any new designs or modifications before committing to any new modifications. QDR Clocking Scheme The controller drives out a pair of K clocks (K and K#), and a pair of C clocks (C and C#).
IXP28XX Network Processor QDR SRAM Table 14. SRAM Controller Configurations Total Number of SRAM Addresses Needed Addresses Used SRAM Size Port-select Pairs Configuration to Index SRAM as Port-enables Available 512K x 18 1 Mbyte 17:0 23:22, 21:20 1M x 18...
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IXP28XX Network Processor QDR SRAM Table 16. Total Memory per Channel (Sheet 2 of 2) Number of SRAMs on Channel SRAM Size 8M x 18 16 Mbytes 32 Mbytes 48 Mbytes 64 Mbytes 16M x 18 32 Mbytes 64 Mbytes...
B3414-01 QDR SRAM Interface The IXP28XX network processor has four independent SRAM subsystems, each of which supports pipelined QDRII-synchronous static RAM (QDRII SRAM). There may also be – in addition to or as a replacement for the pipelined QDR SRAM – a coprocessor with QDR signaling capability.
When using x18 parts with four-SRAM load topology, there are serious signal integrity issues in the DATA-READ cycle when one of the SRAMs is sending data and the IXP28XX network processor is receiving (reading) the data from the SRAM that is driving. For example, the three stubs of the other non-sending SRAMs could cause severe signal reflections that would deteriorate the noise margin as well as the timing in the signal.
IXP28XX Network Processor QDR SRAM 4.4.2 Signal Groups The QDR interface has six groups of signals. These are the K-Clocks, the C-Clocks, Address, Data-OUT or WRITE, Data-IN or READ, and Control. The Control group has three signals, the WRITE PORT ENABLE Active Low, the READ PORT ENABLE Active Low, and the BYTE WRITE ENABLE Active Low.
4.4.5.2 IXP2800 Output Timing The IXP28XX network processor output timings provide for the output timing requirements of the network processor’s driver when it is sending data to the QDR SRAM (Receiver) in the ADDRESS, WRITE, and CONTROL operations. The setup-and-hold time requirements of the receiver (QDR SRAM) side needed for these operations is described in the specification sheet of the SRAM provided by the SRAM manufacturer.
SRAM device. This allows the control and data signals to reach the pins of the SRAM and the IXP28XX network processor (for read) at the same time. In the case of read data being returned to the IXP28XX network processor this makes it easy to find a common data valid window for all signals to be captured by the controller.
IXP28XX Network Processor QDR SRAM P refers to the package length. Figure 33 illustrates routing for QDR Q signal trace width/spacing. Figure 33. QDR Q Signal Trace Width/Spacing Routing POWER or GND Plane 20 mil or larger Other DATA DATA...
IXP28XX Network Processor QDR SRAM Figure 35. QDR K and K# Signal Trace Width/Spacing Routing POWER or GND Plane 20 mil or larger Other K, C Clk K, C Clk signal Signals Signal Signal Prepreg POWER or GND Plane 3994-01 Table 26 lists the QDR K-Clock stack-up signal cross-section details.
±25 mils. However, the individual trace length of each CIN-Clock must be controlled according to the following CIN-Clk/Q relationship formula: CIN/CIN#-Clk-trace-length (SRAM pin to IXP28XX C-IN pin) = Q-trace-length Hardware Design Guide Downloaded from Elcodis.com...
IXP28XX Network Processor QDR SRAM 4.5.7 QDR SRAM RPE#, WPE#, BWE# Control Topologies There are three types of control signals, and each is active low: Write Port Enable (WPE#), Read Port Enable (RPE#), and Byte Write Enable (BWE#). These signals have to be carefully connected, depending on how the four SRAMs are configured.
IXP28XX Network Processor QDR SRAM Table 29. QDR Control RPE# and WPE# Signal Group Routing Guidelines (Sheet 2 of 2) Parameter Routing Guideline Group Spacing Isolation from all other signals is 20 - 25mils. Should be matched to K-Clk trace length minus 0.5 inches.
IXP28XX Network Processor QDR SRAM Figure 41. Control BWE# Signal Trace Width/Spacing Routing POWER or GND Plane 20 mil or larger Other CONTROL CONTROL signal Signals Signal Signal Prepreg POWER or GND Plane 3995-01 Table 32 lists the QDR CONTROL stack-up signal cross-section details.
QDRII-LA1-compliant coprocessor or an upgradable QDR memory module. The Intel BKM for this is to provide the IXP28XX QDR interface through a 2 x 57 shrouded 114-pin Mictor* connector. The connector has all the QDR signals from a single channel and JTAG interface.
IXP28XX breakout guideline 3.5 mils with 4 mil space for a maximum of 400 mils A or B trace length Maximum = 5.0 inches (IXP28XX pin to Mictor* pin) The trace length from ball-to-ball should be within 25 mils. 4.7.1.1.2...
IXP28XX breakout guideline 3.5 mils with 4-mil space for a maximum of 400 mils A or B trace length Maximum = 5.0 inches (IXP28XX pin to Mictor* pin) The trace length from ball-to-ball should be within 25 mils. Hardware Design Guide Downloaded from Elcodis.com...
SRAM causes a reflection that effectively reduces the data-valid window. The maximum operating frequency is effectively, approximately 167 MHz. The following are routing recommendations for four QDR SRAM topologies: • Only terminate lines on IXP28XX network processor drives. • OUTCLK/OUTCLK_L is 4.5 inches. •...
Using one clock pair (C_H[0], C_L[0], K_H[0], K_L[0]) from the IXP28XX network processor to drive the SRAM devices and the other pair (C_H[1], C_L[1]) to clock the Q data back into the IXP28XX network processor, provides the widest timing margin.
C/C# K/K# CQ/CQ# Loopback Clock 3360-01 Figure 50 illustrates the trace length from the IXP28XX network processor to SRAM (C, K, SA, D, and R/W_BW). Figure 51 illustrates the trace length from SRAM to the IXP28XX network processor (Q data).
Q data, even though they follow different paths. In the case of the loopback clock, only the C clock length from the IXP28XX network processor to SRAM and the Q data length from SRAM to the network processor need to be considered. It is assumed that the total C and C_N etch lengths are identical.
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C[0] is two SRAMs for 10 pF (minimum) and 12 pF (maximum). The total capacitive load at the end of the line on Q is one IXP28XX network processor for 5 pF (minimum) and 10 pF (maximum). The total capacitive load at the end of the line on C[1] is one IXP28XX network processor for 5 pF (minimum) and 10 pF (maximum).
QDR SRAM and TCAM Routing The following figures illustrate QDR SRAM and TCAM routing: • Figure 56, “QDR Signal from IXP28XX Network Processor to Tee Point on Layer 12” • Figure 57, “QDR Signal Tee Point Arms Routed on Signal Layers 4 and 13”...
Check for proper ZQ resistor: 50 Ω. • • QDR JTAG pins are 3.3 V on the IXP28XX network processor, but 1.5 V on QDR devices, i.e., a level-shift is necessary. • The IXP28XX network processor CIN[1] pins are NC from the I/O pad to the SRAM controller internally.
IXP28XX Network Processor QDR SRAM 4.12 Package Trace Lengths for QDR Signals Table 35 provides package trace lengths for QDR signals, listed by decreasing lengths in a given logical grouping. Signals in boldface type within the table indicate the start of a logical grouping.
IXP28XX Network Processor QDR SRAM Table 35. Package Trace Lengths for QDR Signals (Sheet 1 of 4) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) QDR0_Q_H[16] 15.959 0.628...
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IXP28XX Network Processor QDR SRAM Table 35. Package Trace Lengths for QDR Signals (Sheet 2 of 4) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) QDR3_Q_H[13] 14.583 0.574...
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IXP28XX Network Processor QDR SRAM Table 35. Package Trace Lengths for QDR Signals (Sheet 3 of 4) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) QDR1_K_H[1] 11.5 0.453...
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IXP28XX Network Processor QDR SRAM Table 35. Package Trace Lengths for QDR Signals (Sheet 4 of 4) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) QDR3_D_H[9] 15.749 0.620...
MSF (SPI-4/CSIX/FC) Media and Switch Fabric Interface ® ® The Media and Switch Fabric (MSF) Interface connects the Intel IXP2800 or Intel IXP2850 Network Processor to a physical layer device (PHY) and/or a Switch Fabric Interface. The MSF consists of the following external interfaces: •...
IXP28XX Network Processor MSF (SPI-4/CSIX/FC) Figure 58. SPI-4 Clock Configuration for Dual Network Processors IXP2800 #1 IXP2800 #2 RD CLK TD CLK RD CLK TD CLK RCLK REF TCLK REF RCLK REF TCLK REF A9317-01 Note that when chaining clocks the jitter accumulated from the MAC, PCB, and RCLK/TCLK_REF pins must be accounted in addition to the duty-cycle distortion.
IXP2800 or IXP2850 network processor sends incoming and outgoing Link Level flow control information across the Flow Control Serial Bus to the ingress IXP28XX network processor. When the IXP2800 or IXP2850 network processor is configured in Simplex Mode, the Flow Control Bus signals are connected directly to the Switch Fabric.
IXP28XX Network Processor MSF (SPI-4/CSIX/FC) Routing Recommendations for LVDS Signals 5.2.1 LVDS Trace Requirements The following is a list of LVDS trace requirements: • Differential signals must be routed as pairs with a 100-Ω differential impedance. • Each leg of a differential pair should be matched by length, within a tolerance of 10 mils.
Terminate unused inputs to their inactive states by using the termination guide above. Termination rules are also discussed in detail in the MSF pin description section of the Intel® IXP2800 and Intel® IXP2850 Network Processors Datasheet. 5.2.4 LVDS Routing Example Figure 60 illustrates LVDS routing as signal pairs with 15-mil trace spacing and an 11-mil air gap.
MSF (SPI-4/CSIX/FC) Simulation Results for LVDS Signals on IXDP2800 Advanced Development Platform Figure 61 illustrates the connections between the IXP28XX network processor and an LVDS load device showing two unique, connected PCBs: Figure 61. Topology 1 - Two Unique PCBs Connected Topology 1 Two unique PCBs connected via a connector.
IXP28XX Network Processor MSF (SPI-4/CSIX/FC) Figure 62. Topology 2 - Two Unique PCBs with Signal Loopback Through Connectors Topology 2 Two unique PCBs and the signal loops from PCB1 to PCB2 back to PCB1 with a connector in each path.
IXP28XX Network Processor MSF (SPI-4/CSIX/FC) Package Trace Lengths for LVDS_Diff Signals Table 38 provides package trace lengths for LVDS_Diff signals, listed by decreasing lengths. For designs that implement dynamic deskew via training, matching of trace lengths through the package is not required as the deskew logic will correct this mismatch. For designs that implement static deskew, trace length-matching through the package may be required.
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IXP28XX Network Processor MSF (SPI-4/CSIX/FC) Table 38. Package Trace Lengths for LVDS_Diff Signals (Sheet 2 of 2) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) SPI4_TPROT_L 12.448 0.490...
In this implementation, both the ingress and egress network processors provide their PCI request signals as output to the 21555 and use the 21555’s grant signals as inputs. The PCI Bus in the IXP28XX network processor is a CMOS bus and is based on reflected wave rather than incident wave signaling.
PPCI Bus Interface The Primary PCI (PPCI) bus is a 64-bit PCI bus that can operate at 33 or 66 MHz. This bus connects the ingress and egress IXP28XX network processor to the master and slave PCI-PCI bridge chips. 6.2.1.1...
IXP28XX Network Processor 6.2.2 SPCI Bus Interface The Secondary PCI interface is a 32-bit bus operating at 33 MHz. This bus starts from the 21154 master PCI-PCI bridge chip. 6.2.2.1 SPCI Address/Data Signals Figure 67 illustrates the topology for SPCI address/data signals.
IXP28XX Network Processor Table 42. SPCI Address/Data Group Guidelines (Sheet 2 of 2) Parameter Routing Guidelines Trace Length A Maximum = 4300 mils Trace Length B Maximum = 200 mils Trace Length C Maximum = 5200 mils Trace Length D...
IXP28XX Network Processor Table 44 provides routing guidelines for the SPCI address/data signals with IDSEL group parameters. Table 44. SPCI Address/Data Signals with IDSEL Group Guidelines Parameter Routing Guidelines Signal Group SPCI Address/Data with IDSEL Topology Daisy Chain Reference Plane Dual-referenced, PWR–SIG–GND...
IXP28XX Network Processor 6.2.3 cPCI Bus Interface The compact PCI (cPCI) interface can be a 32- or 64-bit bus, which can operate at either 33 or 66 MHz. When the base card is not connected to a host, V for this bus comes from the base card 3.3 V power supply.
PCI Routing Examples: IXP2800 Network Processor Figure 72 illustrates 64-bit PCI bus routing between processors and Figure 73 illustrates 64-bit PCI bus routing from the IXP28XX network processor to a bridge. Hardware Design Guide Downloaded from Elcodis.com electronic components distributor...
IXP28XX Network Processor Figure 73 illustrates 64-bit PCI bus routing from the IXP28XX network processor to the bridge. Figure 73. 64-bit PCI Bus Routing from IXP28XX Network Processor to Bridge 64-bit PCI bus routing from IXP28XX Network Processor to bridge...
IXP28XX Network Processor Package Trace Lengths for PCI Signals Table 46 provides package trace lengths for PCI signals. Note: It is typically not required to account for the package trace length for PCI interface signals. The flight time on the package substrate is 154ps/in which differs from the flight delay of standard FR4, typical 180ps/in.
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IXP28XX Network Processor Table 46. Package Trace Lengths for PCI Signals (Sheet 2 of 2) Metric English Metric English Metric English Signal Units Units Signal Units Units Signal Units Units (mm) (in) (mm) (in) (mm) (in) PCI_AD[29] 15.481 0.609 PCI_AD[59] 15.545...
– see Figure 74 (note that the ACK signal is optional). Note: To meet interface timing requirements, Intel suggests the external interface logic be implemented in a high speed CPLD (Complex Programmable Logic Device), as shown in Figure Figure 74.
Access to each of these interfaces is differentiated by two chip selects, SP_CS[n]. External decode logic is required to latch the address and data. Examples of the Slowport interface configuration on the IXP28XX network processor is shown in Figure 75...
IXP28XX Network Processor Slowport 7.1.1 Slowport Signals The Slowport signals are defined in Table 47; Slowport signals use LVTTL signal levels. Table 47. Signal Description Signal Name Description SP_AD[7:0] Address and Data multiplexed bidirectional tri-state busses SP_OE_L Output enable for external buffer SP_CP/SP_A0 Latch enable for 16- or 32-bit data bus devices.
SP_CS[0], while access to the upper 32-Mbyte region of microprocessor space is decoded with SP_CS[1]. Using these two signals, the glue logic distinguishes between accesses to each interface. Refer to the Intel® IXP2800 Network Processor Hardware Reference Manual for additional details about the Slowport unit.
The least significant byte (LSB) of the address is delivered first and the most significant byte (MSB) is presented last. Note: Timing diagrams for all supported modes are provided in the Slowport unit section of the Intel® IXP2800 Network Processor Hardware Reference Manual. We recommend that you consult the HRM and review all of the timing diagrams in that section.
Microprocessor Interface Logic The Slowport microprocessor interface can be configured to support 8-, 16-, and 32-bit devices. Refer to the Intel® IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual for detailed information about each mode. As with the flash interface, external logic must be implemented to latch the address. Since this...
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IXP28XX Network Processor Slowport Example 2. Microprocessor Address Latch Logic // implementation of 25-bit address packing control logic always @(posedge sp_clk) begin if (~rst_l) begin ale_cnt <= 2'b00; else begin if (~sp_ale_l)begin ale_cnt <= ale_cnt + 1; else if (sp_ale_l) begin ale_cnt <= 2'b00;...
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7.1.2.2.3 Write Transactions During write transactions to 16- and 32-bit devices, the 8-bit data from the IXP28XX SP_AD bus must be packed into 16 bits (WORD) or 32 bits (DWORD). Extra signals, SP_CP, SP_OE_L, and SP_DIR, provide the management of packing and unpacking operations and control which device drives the bus during read and write transactions.
SP_WR_L B0600-01 To pack the 32-bit write data, the IXP28XX network processor drives a byte of write data onto the SP_AD bus in four cycles that are qualified with the rising edge of the SP_CP signal, with the SP_OE_L && SP_DIR signal being active, i.e., SP_OE_L = 0 and SP_DIR = 1. On every rising edge of the SP_CP signal with SP_OE_L &&...
IXP28XX Network Processor Slowport Figure 86 is a Slowport Mode 3 Write example with TXE +1 delay using SP_TXE. Figure 86. Slowport Mode 3 write example showing TXE +1 delay using SP_TXE 23 24 CPP_CLK Internal bus clock SP_CLK Rise of SP_CLK...
As with the write operations, the read transactions to 16- and 32-bit devices will need to be unpacked: eight bits per cycle prior to the data being sent back to the IXP28XX network processor via the SP_AD bus. Again, the SP_CP, SP_OE_L, and SP_DIR signals implement the control logic needed to perform the unpacking of the read data.
32-bit register. After the data is captured, the logic must also unpack the data back to the IXP28XX network processor at eight bits per transfer (MSB to LSB) onto the SP_AD. This is accomplished by the glue logic driving the first byte of the read data back to the network processor on the SP_RD_OUT bus when the signal SHIFT_EN is asserted.
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On the clock cycle after the read signal is de-asserted from the downstream device, the glue logic will drive the first byte of data onto the SP_AD bus since the IXP28XX network processor does not pulse the SP_CP signal to promote the first read. The remaining three bytes of data are shifted out on the rising edge of the SP_CP signal to complete the 32-bit transfer.
The data packing/unpacking logic examples were chosen to provide an interface to an Intel/AMCC* device. While the other modes have subtle protocol and interface signal differences, the logic used for address latching and data packing/unpacking should be essentially the same.
IXP28XX Network Processor Mechanical/Packaging Mechanical/Packaging Package Marking ® ® The Intel IXP2800 Network Processor package marking is shown in Figure 89, and the Intel IXP2850 Network Processor package marking is shown in Figure Marketing Product Name Stepping QDF Number Version...