Intel 845 - DESIGN GUIDE Design Manual

Processor in 478-pin package 845 chipset platform for sdr

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Intel

Pentium

478-pin Package and Intel

Chipset Platform for SDR

Design Guide Update

March 2004

Notice: The Intel

845 chipset family may contain design defects or errors known as errata which

may cause the product to deviate from published specifications. Current characterized errata are

documented in the Specification Update.

4 Processor in

845

Document Number:

250425-003

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Summary of Contents for Intel 845 - DESIGN GUIDE

Page 1 ® ® Intel Pentium 4 Processor in ® 478-pin Package and Intel Chipset Platform for SDR Design Guide Update March 2004 ® Notice: The Intel 845 chipset family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in the Specification Update.
Page 2 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Page 3: Table Of Contents
Preface Contents Preface ............................5 Nomenclature........................5 Codes Used in Summary Table ..................6 General Design Considerations ......................... 7 Schematic, Layout, and Routing Updates ....................9 Documentation Changes .......................... 11 Design Guide Update...
Page 4: Revision History
Date -001 Initial Release March 2002 -002 (1) Added Documentation Change #3, Replace Figure 118, Intel® May 2002 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map (2) Added Documentation Change #4, Added Section 4.6.7, Electrostatic Discharge Platform Recommendations...
Page 5: Preface
Nomenclature General Design Considerations include system level considerations that the system designer should account for when developing hardware or software products using the Intel® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR. Schematic, Layout, and Routing Updates include suggested changes to the current published schematics or layout, including typos, errors, or omissions from the current published documents.
Page 6: Codes Used In Summary Table
DOCUMENTATION CHANGES Change Section 12.4.2, 3.3V/V5REF Sequencing Change Section 14.8, Power and Ground, V5REF_SUS Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map Add Section 4.6.7, Electrostatic Discharge Platform Recommendations Change Table 3, System Bus Routing Summary for the Processor Add Section 13.2, Intel®...
Page 7: General Design Considerations
General Design Considerations General Design Considerations There are no General Design Considerations in this Design Guide Update revision. Design Guide Update...
Page 8 General Design Considerations This page is intentionally left blank. Design Guide Update...
Page 9: Schematic, Layout, And Routing Updates
Processor in 478-Pin Package and Intel® 845 Chipset Platform for SDR Design Guide, 298354- 002, dated January 2002. Sheet 11 of the “Intel® 845 SDR Schematics Rev 1.3” contains a circuit at grid location C-7. This circuit has a VCCP input and an HSWING output. Capacitor C5D6 is shown as a series capacitor between VCCP and the HSWING output.
Page 10 Schematic, Layout, and Routing Updates This page is intentionally left blank. Design Guide Update...
Page 11: Documentation Changes
Replaced: Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map, in Section 12.2, is replaced with the following new Power Delivery Map:...
Page 12 ICH2 Resume I/O 3.3V ® Intel ICH2 RTC 3.3V ® ICH2 V5REF Intel Intel ® ICH2 V5REF_SUS FWH 3.3V LPC Super I/O 3.3V CK-408 3.3V Electrostatic Discharge Platform Recommendations The following new material is added as Section 4.6.7, Electrostatic Discharge Platform Recommendations: 4.6.7 Electrostatic Discharge Platform Recommendations...
Page 13 Documentation Changes Intel recommends that the I/O area on the top and bottom signal layers of a 4-layer motherboard near the I/O back panel be filled with a ground fill as shown in Figures 1-4. In addition, a ground fill cutout should be placed on the Vcc layer in the area where the ground fill is done on the top and bottom layers.
Page 14 Add Section 13.2, Intel® Boxed Processor Mechanical Keep-Outs The following new section is added: 13.2 Intel® Boxed Processor Mechanical Keep-Outs Verify Intel’s Boxed Processor mechanical keep-outs are marked and visible during board layout. This keep-out zone should be considered during chassis selection. Design Guide Update...
Page 15: Signal Description
15.1.3 Intel® Boxed Processor Mechanical Keep-Outs Checklist Item Intel® Boxed Processor Mechanical Keep-Outs • Verify Intel’s Boxed Processor mechanical keep-outs are marked and visible during board layout. This keep-out zone should be considered during chassis selection. Revise Section 14.1, Schematic Checklist, Host Interface, PWRGOOD Revise Section 14.1, Schematic Checklist, Host Interface, PWRGOOD with the following:...

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