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HARDWARE REFERENCE
3.12.1.4
Expansion ROM Region Configuration
The PCI specification allows expansion boards to include device-specific initialization code in PCI
expansion ROM, which is executed at start-up on the host system. Expansion ROM on the PCI-SDK
Platform can be configured as a PCI expansion ROM region by programming two Local Configuration
registers on the PCI 9060. The Local Base Address for PCI-to-Local Expansion ROM and BREQo
Control Register (94H) (see Table 3-27) should be programmed with the base address of the expansion
ROM on the local bus.
Initialization code should clear as many bits in the Range for PCI-to-Local Expansion ROM Register
(90H) (see Table 3-26) as necessary to address the ROM region; the remaining upper bits should be set.
Unlike RAM region remapping, the ROM region is enabled by default. To disable the ROM region, user
code should clear the Enable bit in the PCI Base Address to Local Expansion ROM (30H) and clear the
Local Base Address Register (94H).
The Local Bus Region Descriptor for PCI-to-Local Accesses Register (98H) contains control settings
for the expansion ROM region. Table 3-25 shows the settings required for a ROM region on the PCI-
SDK Platform. See Section 3.12.1.5, Memory Region Configuration Examples (pg. 3-22) for an illus-
tration of the expansion ROM region configuration.
3.12.1.5
Memory Region Configuration Examples
MON960 determines the size of installed DRAM and configures the DRAM as a PCI memory region.
Suppose 8 Mbytes of DRAM are located at local address A0000000H through A07FFFFFH. To
configure this region to be visible in memory space on the PCI bus, the following register settings must
be made:
Local Address Space 0 Range Register (80H) - FF800000H
•
An 8 Mbyte space is being mapped, so the lower 23 bits are needed to decode an access and
must be clear. The upper 9 (set) bits of a PCI-to-local access to this region are replaced with the
contents of the Local Address Space 0 Local Base Address Register (84H). Bit 0 is clear, so
memory is mapped into PCI memory space. Bits 1 and 2 are clear, so the host system maps this
region anywhere in 32-bit PCI address space. Bit 3 is clear, indicating that the memory in this
region is not pre-fetchable.
3-22
Table 3-25. ROM Region Settings
Bits
Function
1:0
Bus Width
5:2
Internal Wait States
6
READY Input Enable
7
BTERM Input Enable
Setting
11 (32 Bit Bus Width)
0 (No Wait States)
1 (Enabled)
0 (Disabled)
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