Clocked Mode; Strobed Mode; Configuration Of Memory Bus Mode; Snoop Modes - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
signals. The cycle control signals are synchronous with the CPU/cache core clock frequency
(CLK). The CPU and memory address path signals are synchronous to CLK during normal
read, write, and replacement write-back cycles. Address control signals are asynchronous.
Snoop address control signals, depending upon the snoop mode, may be asynchronous or
synchronous to SNPCLK during snoop operations.
4.3.1.1.
CLOCKED MODE
In clocked memory bus mode, the Memory Bus Controller (MBC) provides the 82491 Cache
SRAM with a memory clock (MCLK) input which drives and provides sampling times for all
data path signals. The system designer can select from one of three MCLK frequencies:
MCLK = CLK This selection provides a synchronous memory bus. Because all signals
are driven at very HIGH frequencies, memory bus logic is fast and
complex. However, this selection eliminates the need for a
synchronization interface between memory bus and cycle control signals.
MCLK*N = CLK This selection provides a divided synchronous memory bus. The memory
bus operates at a reduced speed, thereby simplifying design, while only
minimal synchronization is needed to interface memory bus and cycle
control signals.
MCLK
< CLK
This selection provides an asynchronous memory bus. MCLK may be
any frequency that optimizes the memory bus. Synchronization is
required to interface memory bus and cycle control signals.
4.3.1.2.
STROBED MODE
In strobed memory bus mode, all signals are related to other signals. Clocks are not used to
control the data path. For example, data may be strobed into the 82491 Cache SRAM accord-
ing to the rising and falling edges of MISTB. Because operation is based on handshaking,
strobed mode eliminates the need for clocks and clock skews. Strobed mode does require
synchronization in interfacing memory bus and cycle control signals.
4.3.1.3.
CONFIGURATION OF MEMORY BUS MODE
To put the 82491 Cache SRAM into the Clocked Memory Bus Mode, the memory bus
controller (MBC) supplies a clock input to the MCLK pin, which the 82491 Cache SRAM
detects at reset. If MCLK is driven HIGH or LOW (MSTBM) at reset, the 82491 Cache SRAM
enters Strobed Memory Bus Mode.
4.3.2. Snoop Modes
The 82496 Cache Controller can be configured to one of three different snoop modes. The
snoop mode determines how the MBC initiates a snoop to the cache. Regardless of the snoop
initiation mode, the 82496 Cache Controller responds to snoops synchronous to CLK.
Snooping may be initiated in Synchronous, Clocked or Strobed Snoop Modes. The snoop
mode is not related to the memory bus mode selected for the 82491 Cache SRAM (data path).
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