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Intel 386 User Manual

Intel 386 User Manual

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Summary of Contents for Intel 386

Page 1 Intel386 Embedded Microprocessor User’s Manual ™ Intel386 EXTB Embedded Microprocessor ™ Intel386 EXTC Embedded Microprocessor ™...
Page 2 ™ Intel386 EX Embedded Microprocessor User’s Manual 1996...
Page 3 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in- fringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Page 4: Table Of Contents
CHAPTER 1 GUIDE TO THIS MANUAL MANUAL CONTENTS ... 1-1 NOTATIONAL CONVENTIONS... 1-3 SPECIAL TERMINOLOGY ... 1-4 RELATED DOCUMENTS ... 1-5 ELECTRONIC SUPPORT SYSTEMS ... 1-6 1.5.1 FaxBack Service ...1-6 1.5.2 Bulletin Board System (BBS) ...1-7 1.5.3 CompuServe Forums ...1-7 1.5.4 World Wide Web ...1-7 TECHNICAL SUPPORT ...
Page 5 Intel386™ EX MICROPROCESSOR USER’S MANUAL 4.5.2 Enabling and Disabling the Expanded I/O Space ...4-8 4.5.2.1 Programming REMAPCFG Example ...4-8 ADDRESSING MODES ... 4-9 4.6.1 DOS-compatible Mode ...4-9 4.6.2 Nonintrusive DOS Mode ...4-11 4.6.3 Enhanced DOS Mode ...4-11 4.6.4 Non-DOS Mode ...4-11 PERIPHERAL REGISTER ADDRESSES...
Page 6 6.3.4 Interrupt Acknowledge Cycle ...6-23 6.3.5 Halt/Shutdown Cycle ...6-26 6.3.6 Refresh Cycle ...6-28 6.3.7 BS8 Cycle ...6-31 6.3.7.1 Write Cycles ...6-31 6.3.7.2 Read Cycles ...6-31 BUS LOCK... 6-34 6.4.1 Locked Cycle Activators ...6-34 6.4.2 Locked Cycle Timing ...6-34 6.4.3 LOCK# Signal Duration ...6-35 EXTERNAL BUS MASTER SUPPORT (USING HOLD, HLDA)...
Page 7 Intel386™ EX MICROPROCESSOR USER’S MANUAL 7.3.4.2 SMRAM State Dump Area ...7-14 7.3.5 Resume Instruction (RSM) ...7-15 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS ... 7-15 PROGRAMMING CONSIDERATIONS... 7-16 7.5.1 System Management Mode Code Example ...7-16 CHAPTER 8 CLOCK AND POWER MANAGEMENT UNIT OVERVIEW ...
Page 8 9.3.3 Initialization Command Word 1 (ICW1) ...9-20 9.3.4 Initialization Command Word 2 (ICW2) ...9-21 9.3.5 Initialization Command Word 3 (ICW3) ...9-22 9.3.6 Initialization Command Word 4 (ICW4) ...9-24 9.3.7 Operation Command Word 1 (OCW1) ...9-25 9.3.8 Operation Command Word 2 (OCW2) ...9-26 9.3.9 Operation Command Word 3 (OCW3) ...9-27 9.3.10...
Page 9 Intel386™ EX MICROPROCESSOR USER’S MANUAL CHAPTER 11 ASYNCHRONOUS SERIAL I/O UNIT 11.1 OVERVIEW ... 11-1 11.1.1 SIO Signals ...11-3 11.2 SIO OPERATION ... 11-4 11.2.1 Baud-rate Generator ...11-4 SIO n Transmitter ...11-6 11.2.2 SIO n Receiver ...11-9 11.2.3 11.2.4 Modem Control ...11-12 11.2.5 Diagnostic Mode ...11-12 11.2.6...
Page 10 12.2.4 Bus Control Arbitration ...12-9 12.2.5 Ending DMA Transfers ...12-10 12.2.6 Buffer-transfer Modes ...12-12 12.2.6.1 Single Buffer-Transfer Mode ...12-12 12.2.6.2 Autoinitialize Buffer-Transfer Mode ...12-12 12.2.6.3 Chaining Buffer-Transfer Mode ...12-12 12.2.7 Data-transfer Modes ...12-13 12.2.7.1 Single Data-transfer Mode ...12-14 12.2.7.2 Block Data-transfer Mode ...12-18 12.2.7.3 Demand Data-transfer Mode ...12-21 12.2.8...
Page 11 Intel386™ EX MICROPROCESSOR USER’S MANUAL 13.2.3 Receiver ...13-12 13.3 REGISTER DEFINITIONS... 13-16 13.3.1 Pin Configuration Register (PINCFG) ...13-17 13.3.2 SIO and SSIO Configuration Register (SIOCFG) ...13-18 13.3.3 Prescale Clock Register (CLKPRS) ...13-19 13.3.4 SSIO Baud-rate Control Register (SSIOBAUD) ...13-20 13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) ...13-21 13.3.6 SSIO Control 1 Register (SSIOCON1) ...13-21...
Page 12 15.2.3 Refresh Addresses ...15-4 15.2.4 Bus Arbitration ...15-5 15.3 RCU OPERATION ... 15-5 15.4 REGISTER DEFINITIONS... 15-6 15.4.1 Refresh Clock Interval Register (RFSCIR) ...15-7 15.4.2 Refresh Control Register (RFSCON) ...15-8 15.4.3 Refresh Base Address Register (RFSBAD) ...15-9 15.4.4 Refresh Address Register (RFSADD) ...15-10 15.5 DESIGN CONSIDERATIONS...
Page 13 Intel386™ EX MICROPROCESSOR USER’S MANUAL CHAPTER 18 JTAG TEST-LOGIC UNIT 18.1 OVERVIEW ... 18-1 18.2 TEST-LOGIC UNIT OPERATION... 18-3 18.2.1 Test Access Port (TAP) ...18-3 18.2.2 Test Access Port (TAP) Controller ...18-4 18.2.3 Instruction Register (IR) ...18-7 18.2.4 Data Registers ...18-8 18.3 TESTING ...
Page 14 APPENDIX D SYSTEM REGISTER QUICK REFERENCE PERIPHERAL REGISTER ADDRESSES... D-1 CLKPRS ... D-7 CS n ADH (UCSADH)... D-8 CS n ADL (UCSADL) ... D-9 CS n MSKH (UCSMSKH) ... D-10 CS n MSKL (UCSMSKL) ... D-11 DLL n AND DLH n ... D-12 DMABSR ...
Page 15 Intel386™ EX MICROPROCESSOR USER’S MANUAL D.37 OCW1 (MASTER AND SLAVE)... D-40 D.38 OCW2 (MASTER AND SLAVE)... D-41 D.39 OCW3 (MASTER AND SLAVE)... D-42 D.40 P1CFG ... D-43 D.41 P2CFG ... D-44 D.42 P3CFG ... D-45 D.43 PINCFG ... D-46 D.44 P n DIR ...
Page 16 APPENDIX E INSTRUCTION SET SUMMARY INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY... E-1 INSTRUCTION ENCODING ... E-22 E.2.1 32-bit Extensions of the Instruction Set ... E-23 E.2.2 Encoding of Instruction Fields ... E-24 E.2.2.1 Encoding of Operand Length (w) Field ... E-24 E.2.2.2 Encoding of the General Register (reg) Field ...
Page 17 Intel386™ EX MICROPROCESSOR USER’S MANUAL Figure Intel386™ EX Embedded Processor Block Diagram ...2-2 Instruction Pipelining ...3-2 The Intel386™ CX Processor Internal Block Diagram ...3-3 PC/AT I/O Address Space (10-bit Decode) ...4-3 Expanded I/O Address Space (16-bit Decode) ...4-4 Address Configuration Register (REMAPCFG)...4-7 Setting the ESE Bit Code Example ...4-8 DOS-Compatible Mode ...4-10 Example of Nonintrusive DOS-Compatible Mode ...4-12...
Page 18 Figure 6-16 Intel386 EX Processor to SRAM/FLASH Interface...6-41 6-17 Intel386 EX Processor to PSRAM Interface ...6-42 6-18 Intel386 EX Processor to Paged DRAM Interface...6-43 6-19 Intel386 EX Processor and Non-Paged DRAM Interface ...6-44 Standard SMI# ...7-5 SMIACT# Latency ...7-6 SMI# During HALT ...7-8 SMI# During I/O Instruction ...7-9 SMI# Timing ...7-10 Interrupted SMI# Service...7-11...
Page 19 Intel386™ EX MICROPROCESSOR USER’S MANUAL Figure 10-7 Mode 1 – Writing a New Count...10-10 10-8 Mode 2 – Basic Operation ...10-11 10-9 Mode 2 – Disabling the Count ...10-11 10-10 Mode 2 – Writing a New Count...10-12 10-11 Mode 3 – Basic Operation (Even Count)...10-13 10-12 Mode 3 –...
Page 20 Figure 11-21 Modem Control Register (MCR n ) ...11-30 11-22 Modem Status Register (MSR n )...11-31 11-23 Scratch Pad Register (SCR n )...11-32 12-1 DMA Unit Block Diagram...12-2 12-2 DMA Temporary Buffer Operation for a Read Transfer...12-8 12-3 DMA Temporary Buffer Operation for A Write Transfer ...12-8 12-4 Start of a Two-cycle DMA Transfer Initiated by DRQ n ...12-9 12-5...
Page 21 Intel386™ EX MICROPROCESSOR USER’S MANUAL Figure 13-7 SSIO Transmitter with Autotransmit Mode Disabled ...13-8 13-8 Transmit Data by Polling ...13-9 13-9 Interrupt Service Routine for Transmitting Data Using Interrupts...13-10 13-10 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is High) ...13-11 13-11 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is Low) ...13-11 13-12...
Page 22 Figure 17-4 WDT Reload Value Registers (WDTRLDH and WDTRLDL)...17-10 17-5 Power Control Register (PWRCON)...17-11 18-1 Test Logic Unit Connections ...18-2 18-2 TAP Controller (Finite-State Machine)...18-6 18-3 Instruction Register (IR)...18-7 18-4 Identification Code Register (IDCODE) ...18-8 18-5 Internal and External Timing for Loading the Instruction Register...18-12 18-6 Internal and External Timing for Loading a Data Register...18-13 Derivation of AEN Signal in a Typical PC/AT System ...
Page 23 Intel386™ EX MICROPROCESSOR USER’S MANUAL Table PC-compatible Peripherals...2-3 Embedded Application-specific Peripherals ...2-4 Peripheral Register I/O Address Map in Slot 15...4-5 Peripheral Register Addresses...4-15 Master’s IR3 Connections ...5-8 Master’s IR4 Connections ...5-8 Signal Pairs on Pins without a Multiplexer...5-23 Example Pin Configuration Registers...5-30 Example DMACFG Configuration Register ...5-31 Example TMRCFG Configuration Register ...5-32 Example INTCFG Configuration Register ...5-33...
Page 24 Table 13-2 Maximum and Minimum Baud-rate Output Frequencies ...13-6 13-3 SSIO Registers...13-16 14-1 CSU Signals ...14-13 14-2 CSU Registers...14-14 15-1 RCU Signals ...15-4 15-2 RCU Registers ...15-6 16-1 Pin Multiplexing ...16-5 16-2 I/O Port Registers...16-6 16-3 Control Register Values for I/O Port Pin Configurations...16-7 17-1 WDT Signals ...17-3 17-2...
Page 26: Guide To This Manual
GUIDE TO THIS MANUAL...
Page 28: Manual Contents
Chapter 6 — Bus Interface Unit — describes the bus interface logic, bus states, bus cycles, and instruction pipelining. Chapter 7 — System Management Mode — describes Intel’s System Management Mode (SMM). Chapter 8 — Clock and Power Management Unit — describes the clock generation circuitry, power management modes, and system reset logic.
Page 29 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Chapter 9 — Interrupt Control Unit — describes the interrupt sources and priority options and explains how to program the interrupt control unit. Chapter 10 — Timer/Counter Unit — describes the timer/counters and their available count formats and operating modes.
Page 30: Notational Conventions
NOTATIONAL CONVENTIONS The following notations are used throughout this manual. The pound symbol (#) appended to a signal name indicates that the signal is active low. Variables Variables are shown in italics. Variables must be replaced with correct values. New Terms New terms are shown in italics.
Page 31: Special Terminology
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Register Bits When the text refers to more that one bit, the range may appear as two numbers separated by a colon (example: 7:0 or 15:0). The first bit shown (7 or 15 in the example) is the most-significant bit and the second bit shown (0) is the least-significant bit.
Page 32: Related Documents
RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that incorporate the Intel386 EX processor. To order documents, please call Intel Literature Fulfill- ment (1-800-548-4725 in the U.S. and Canada; +44(0) 1793-431155 in Europe). Document Name Intel386™...
Page 33: Electronic Support Systems
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information. Intel also maintains several forums on CompuServe and offers a variety of information on the World Wide Web. These systems are available 24 hours a day, 7 days a week, providing technical information whenever you need it.
Page 34: Bulletin Board System (Bbs)
CompuServe Forums The CompuServe forums provide a means for you to gather information, share discoveries, and debate issues. Type “go intel” for access. For information about CompuServe access and service fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).
Page 35: Product Literature
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL PRODUCT LITERATURE You can order product literature from the following Intel literature centers. 1-800-548-4725 708-296-9333 44(0)1793-431155 44(0)1793-421333 44(0)1793-421777 81(0)120-47-88-32 U.S. and Canada U.S. (from overseas) Europe (U.K.) Germany France Japan (fax only)
Page 36: Architectural Overview
ARCHITECTURAL OVERVIEW...
Page 38: Intel386 Ex Embedded Processor Core
™ The Intel386 EX embedded processor (Figure 2-1) is based on the static Intel386 SX processor. This highly integrated device retains those personal computer functions that are useful in embed- ded applications and integrates peripherals that are typically needed in embedded systems. The Intel386 EX processor provides a PC-compatible development platform in a device that is opti- mized for embedded applications.
Page 39: Intel386™ Ex Embedded Processor Block Diagram
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Intel386 ™ CX Core Core Enhancements - A20 Gate - CPU Reset - SMM INTR Figure 2-1. Intel386™ EX Embedded Processor Block Diagram Bus Interface Unit Chip-select Unit JTAG Unit Address Clock and Power Management Unit DRAM Refresh Data...
Page 40: Integrated Peripherals
INTEGRATED PERIPHERALS The Intel386 EX processor integrates both PC-compatible peripherals (Table 2-1) and peripherals that are specific to embedded applications (Table 2-2). Table 2-1. PC-compatible Peripherals Name Interrupt Consists of two 82C59A programmable interrupt controllers (PICs) configured as master Control Unit and slave.
Page 41: Embedded Application-Specific Peripherals
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 2-2. Embedded Application-specific Peripherals Name System The Intel386 EX processor provides a mechanism for system management with a Management combination of hardware and CPU microcode enhancements. An externally generated Mode (SMM) system management interrupt (SMI#) allows the execution of system-wide routines that are independent and transparent to the operating system.
Page 42: Core Overview
CORE OVERVIEW...
Page 44: Intel386 Cx Processor Enhancements
The Intel386™ EX processor core is based upon the Intel386 CX processor, which is an enhanced version of the Intel386 SX processor. This chapter describes the Intel386 CX processor enhance- ments over the Intel386 SX processor, internal architecture of the Intel386 CX processor, and the core interface on the Intel386 EX processor.
Page 45: Intel386 Cx Processor Internal Architecture
Intel386 CX processor results in higher performance and enhanced throughput rate over non- pipelined processors. Elapsed Time Typical Fetch 1 Decode 1 Processor Intel386™ SX CPU/Intel376™ CPU 386™ SX CPU/376™ CPU Bus Unit Fetch 1 Fetch 2 Decode Decode 1 Unit Execution Unit Figure 3-1.
Page 46: The Intel386™ Cx Processor Internal Block Diagram
Figure 3-2 shows the internal architecture of the Intel386 CX processor. Effective Address Bus Effective Address Bus Protection Test Unit Barrel Decode Shifter, Status Adder Flags Sequencing Multiply/ Divide Control Register File Control Control Figure 3-2. The Intel386™ CX Processor Internal Block Diagram Segmentation Unit Paging Unit 3-Input...
Page 47: Core Bus Unit
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The six functional units of the Intel386 CX processor are: • Core Bus Unit • Instruction Prefetch Unit • Instruction Decode Unit • Execution Unit • Segmentation Unit • Paging Unit 3.2.1 Core Bus Unit The Core Bus Unit provides the interface between the processor and its environment.
Page 48: Execution Unit
3.2.4 Execution Unit The Execution Unit executes the instructions from the Instruction Queue and therefore commu- nicates with all other units required to complete the instruction. The functions of its three subunits are given below. • The Control Unit contains microcode and special parallel hardware that speeds multiply, divide, and effective address calculation.
Page 49: Core Intel386 Ex Processor Interface
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CORE Intel386 EX PROCESSOR INTERFACE The Intel386 EX processor peripherals are connected to the Intel386 CX processor core through an internal Bus Interface Unit (BIU). The BIU controls internal peripheral accesses and external memory and I/O accesses. Because it has the BIU between the Intel386 CX processor core and the external bus, the Intel386 EX processor bus timings are not identical to those of the Intel386 CX processor or Intel386 SX processor.
Page 50: System Register Organization
SYSTEM REGISTER ORGANIZATION...
Page 52: Overview
SYSTEM REGISTER ORGANIZATION This chapter provides an overview of the system registers incorporated in the Intel386™ EX pro- cessor, focusing on register organization from an address architecture viewpoint. The chapters that cover the individual peripherals describe the registers in detail. This chapter is organized as follows: •...
Page 53: Intel386 Processor Core Architecture Registers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL — Power management control registers — Chip-select unit control registers — Refresh control unit registers — Watchdog timer control registers — Synchronous serial I/O control registers — Parallel I/O port control registers 4.1.1 Intel386 Processor Core Architecture Registers These registers are a superset of the 8086 and 80286 processor registers.
Page 54: Expanded I/O Address Space
General Slot I/O Platform I/O (Reserved) General Slot I/O Platform I/O (Reserved) General Slot I/O Platform I/O (Reserved) General Slot I/O Platform I/O (Reserved) Figure 4-1. PC/AT I/O Address Space (10-bit Decode) EXPANDED I/O ADDRESS SPACE The Intel386 EX processor’s I/O address scheme is similar to that of the Extended Industry Stan- dard Architecture (EISA) bus and the Enhanced - Industry Standard Architecture (E-ISA) bus.
Page 55: Expanded I/O Address Space (16-Bit Decode)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL (See Figure 4-2.) Thus, each slot has 1 Kbyte addresses (in four 256-byte segments) that can po- tentially contain extended peripheral registers. General Slot I/O General Slot I/O General Slot I/O General Slot I/O General Slot I/O General Slot I/O General Slot I/O...
Page 56: Organization Of Peripheral Registers
The Intel386 EX processor uses slot 15 for the registers needed for integrated peripherals. Using this slot avoids conflicts with other devices in an EISA system, since EISA systems typically do not use slot 15. ORGANIZATION OF PERIPHERAL REGISTERS The registers associated with the integrated peripherals are physically located in slot 15 of the I/O space.
Page 57: I/O Address Decoding Techniques
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL I/O ADDRESS DECODING TECHNIQUES One of the key features of the Intel386 EX processor is that it is configurable for compatibility with the standard PC/AT architecture. In a PC/AT system, the platform I/O resources are located in the slot 0 I/O address space.
Page 58: Address Configuration Register (Remapcfg)
Address Configuration Register REMAPCFG — — — Number Mnemonic 0 = Disables expanded I/O space 1 = Enables expanded I/O space 14–7 — Reserved. 0 = Makes serial channel 1 (COM2) accessible in both DOS I/O space and expanded I/O space 1 = Remaps serial channel 1 (COM2) address into expanded I/O space 0 = Makes serial channel 0 (COM1) accessible in both DOS I/O space and expanded I/O space...
Page 59: Enabling And Disabling The Expanded I/O Space
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 4.5.2 Enabling and Disabling the Expanded I/O Space The Intel386 EX processor’s expanded I/O space is enabled by a specific write sequence to I/O addresses 22H and 23H (Figure 4-4). Once the expanded I/O space is enabled, internal peripher- als (timers, DMA, interrupt controllers and serial communication channels) can be mapped out of DOS I/O space (using the REMAPCFG register) and registers associated with other internal peripherals (such as the chip-select unit, power management unit, watchdog timer) can be access-...
Page 60: Addressing Modes
SYSTEM REGISTER ORGANIZATION ADDRESSING MODES Combinations of the value of ESE bit and the individual remap bits in the REMAPCFG register yield four different peripheral addressing modes for I/O address decoding. 4.6.1 DOS-compatible Mode DOS-compatible mode is achieved by clearing ESE and all the peripheral remap bits. In this mode, all PC/AT-compatible peripherals are mapped into the DOS I/O space.
Page 61: Dos-Compatible Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3FFH On-chip UART-0 On-chip UART-1 On-chip 8259A-2 On-chip Timer REMAPCFG Register On-chip 8259A-1 DOS I/O Space Figure 4-5. DOS-Compatible Mode 4-10 Expanded I/O Space Note: On-chip DMA Shaded area indicates that expanded I/O space peripherals are not accessible FFFFH F000H...
Page 62: Nonintrusive Dos Mode
4.6.2 Nonintrusive DOS Mode This mode is achieved by first setting the ESE bit (using the three sequential writes), setting the individual peripherals’ remap bits, and then clearing the ESE bit. Peripherals whose remap bits are set are mapped out of DOS I/O space. Like DOS-compatible mode, only address lines A9:0 are decoded internally.
Page 63: Example Of Nonintrusive Dos-Compatible Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3FFH On-chip UART-0 On-chip UART-1 On-chip 8259A-2 On-chip Timer REMAPCFG Register On-chip 8259A-1 DOS I/O Space Figure 4-6. Example of Nonintrusive DOS-Compatible Mode 4-12 Expanded I/O Space Note: Internal DMA Shaded area indicates that the on-chip DMA and expanded I/O space peripherals are not accessible FFFFH...
Page 64: Enhanced Dos Mode
3FFH On-chip UART-2 On-chip UART-1 On-chip 8259A-2 On-chip Timer REMAPCFG Register On-chip 8259A-1 On-chip DMA DOS I/O Space Figure 4-7. Enhanced DOS Mode SYSTEM REGISTER ORGANIZATION Other Peripherals On-chip DMA Expanded I/O Space FFFFH UART-0 UART-1 Timer 8259A-2 8259A-1 F000H A2501-02 4-13...
Page 65: Nondos Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 3FFH REMAPCFG Register DOS I/O Space 4-14 Other Peripherals Expanded I/O Space Figure 4-8. NonDOS Mode FFFFH UART-0 UART-1 Timer 8259A-2 8259A-1 On-chip DMA F000H A2502-02...
Page 66: Peripheral Register Addresses
PERIPHERAL REGISTER ADDRESSES Table 4-2 lists the addresses and names of all user-accessible peripheral registers. I/O Registers can be accessed as bytes or words. Word accesses to byte registers result in two sequential 8-bit I/O transfers. The default (reset) value of each register is shown in the Reset Value column. An X in this column signifies that the register bits are undefined.
Page 67 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 4-2. Peripheral Register Addresses (Sheet 2 of 6) Expanded PC/AT Address Address F018H F019H F01AH F01BH F01CH F01DH F01EH F020H 0020H F021H 0021H 0022H 0022H F040H 0040H F041H 0041H F042H 0042H F043H 0043H F080H F081H 0081H...
Page 68 Table 4-2. Peripheral Register Addresses (Sheet 3 of 6) Expanded PC/AT Address Address F08DH F08EH F08FH F098H F099H F09AH F09BH F092H 0092H F0A0H 00A0H F0A1H 00A1H F400H F402H F404H F406H F408H F40AH F40CH F40EH F410H F412H F414H F416H F418H F41AH F41CH F41EH F420H...
Page 69 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 4-2. Peripheral Register Addresses (Sheet 4 of 6) Expanded PC/AT Address Address F424H F426H F428H F42AH F42CH F42EH F430H F432H F434H F436H F438H F43AH F43CH F43EH F480H F482H F484H F486H F488H F48AH F4A0H F4A2H F4A4H F4A6H...
Page 70 Table 4-2. Peripheral Register Addresses (Sheet 5 of 6) Expanded PC/AT Address Address F4CAH Asynchronous Serial I/O Channel 0 (COM1) F4F8H 03F8H F4F9H 03F9H F4FAH 03FAH F4FBH 03FBH F4FCH 03FCH F4FDH 03FDH F4FEH 03FEH F4FFH 03FFH Clock Generation and Power Management F800H F804H Device Configuration Registers...
Page 71 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 4-2. Peripheral Register Addresses (Sheet 6 of 6) Expanded PC/AT Address Address Asynchronous Serial I/O Channel 1 (COM2) F8F8H 02F8H F8F9H 02F9H F8FAH 02FAH F8FBH 02FBH F8FCH 02FCH F8FDH 02FDH F8FEH 02FEH F8FFH 02FFH NOTES: Byte pointer in flip-flop in DMA determines which register is accessed.
Page 72: Device Configuration
DEVICE CONFIGURATION...
Page 74: Introduction
The Intel386™ EX processor provides many possible signal to pin connections as well as periph- eral to peripheral connections. This chapter describes the available configurations and how to configure them. This chapter is organized as follows: • Introduction (see below) •...
Page 75: Peripheral And Pin Connections
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Figure 5-1 shows Peripheral A and its connections to other peripherals and the package pins. The “Internal Connection Logic” provides three kinds of connections: • Connections between peripherals • Connections to package pins via multiplexers •...
Page 76: Peripheral Configuration
PERIPHERAL CONFIGURATION This section describes the configuration of each on-chip peripheral. For more detailed informa- tion on the peripheral itself, see the chapter describing that peripheral. The symbology used for signals that share a device pin is shown in Figure 5-2. Of the two signal names by a pin, the upper signal is associated with the peripheral in the figure.
Page 77: Using The Timer To Initiate Dma Transfers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL configured DMA channel. SIO and SSIO inputs to the DMA are selected by the DMA configu- ration register (Figure 5-3). 5.2.1.3 Using The Timer To Initiate DMA Transfers A timer output (OUT1, OUT2) can initiate periodic data transfers by the DMA. A DMA channel is programmed for the transfer, then a timer output pulse triggers the transfer.
Page 78: Configuration Of Dma, Bus Arbiter, And Refresh Unit
DMACFG.2:0 DREQ0 DMACFG.3 DMAACK0# DMACFG.6:4 DREQ1 DMACFG.7 DMAACK1# To ICU DMAINT End of Process HOLD Bus Arbiter Core HOLD HLDA Refresh Unit From REFRESH# Core HLDA † Alternate pin signals are in parentheses. Figure 5-2. Configuration of DMA, Bus Arbiter, and Refresh Unit DEVICE CONFIGURATION RBFDMA0 (SIO0) To SIO1...
Page 79: Dma Configuration Register (Dmacfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DMA Configuration DMACFG (read/write) D1MSK D1REQ2 D1REQ1 Number Mnemonic D1MSK DMA Acknowledge 1 Mask: 0 = DMA channel 1’s acknowledge (DMAACK1#) signal is not masked. 1 = Masks DMA channel 1’s acknowledge (DMAACK1#) signal. Useful 6–4 D1REQ2:0 DMA Channel 1 Request Connection:...
Page 80: Interrupt Control Unit Configuration
5.2.2 Interrupt Control Unit Configuration The interrupt control unit (ICU) comprises two 82C59A interrupt controllers connected in cas- cade, as shown in Figure 5-4. (See Chapter 9 for more information.) Figure 5-5 describes the in- terrupt configuration register (INTCFG). The ICU receives requests from eight internal sources: •...
Page 81: Master's Ir3 Connections
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 5-1. Master’s IR3 Connections Function IR3 connected to SIOINT1 P3.1 selected at pin (P3.1) IR3 connected to SIOINT1 OUT1 connected to pin (TMROUT1) IR3 internally driven low P3.1 selected at pin (P3.1) IR3 connected to pin (INT8) IR3 connected to SIOINT1 P3.1 selected at pin (P3.1) IR3 connected to SIOINT1...
Page 82: Interrupt Control Unit Configuration
8259A P3CFG.2 Master INTCFG.6 INTR core) INTCFG.5 P3CFG.3 P3CFG.4 CAS2:0 P3CFG.5 INTCFG.0 8259A INTCFG.1 Slave OUT1(TCU) OUT2(TCU) INTCFG.4 CAS2:0 INTCFG.2 WDTOUT# † Alternate pin signals are in parentheses Heavier lines indicate multiple signals. Figure 5-4. Interrupt Control Unit Configuration OUT0 (TCU) To/From I/O Port 3 MCR1.3 SIOINT1...
Page 83: Interrupt Configuration Register (Intcfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Interrupt Configuration INTCFG (read/write) Number Mnemonic Cascade Enable: 0 = Disables the cascade signals CAS2:0 from appearing on the A18:16 1 = Enables the cascade signals CAS2:0, providing access to external Internal Master IR3 Connection: See Table 5-1 on page 5-8 for all the IR3 configuration options.
Page 84: Timer/Counter Unit Configuration
DEVICE CONFIGURATION 5.2.3 Timer/counter Unit Configuration The three-channel Timer/counter Unit (TCU) and its configuration register (TMRCFG) are shown in Figure 5-6 and Figure 5-7. The clock inputs can be external signals (TMRCLK2:0) or the on-chip programmable clock (PSCLK). All clock inputs can be held low by programming bits in the TMRCFG register.
Page 85: Timer/Counter Unit Configuration
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Timer/Counter Unit CLKIN0 TMRCFG.6 GATE0 OUT0 CLKIN1 TMRCFG.6 GATE1 OUT1 CLKIN2 TMRCFG.6 GATE2 OUT2 † Alternate pin signals are in parentheses. Figure 5-6. Timer/Counter Unit Configuration 5-12 TMRCFG.7 TMRCFG.0 PSCLK To ICU TMRCFG.1 TMRCFG.1 To ICU To ICU To/From I/O Port 3...
Page 86: Timer Configuration Register (Tmrcfg)
Timer Configuration TMRCFG (read/write) TMRDIS SWGTEN GT2CON Number Mnemonic TMRDIS Timer Disable: 0 = Enables the CLKIN n signals. 1 = Disables the CLKIN n signals. SWGTEN Software GATE n Enable 0 = Connects GATE n to either the V 1 = Enables GT2CON, GT1CON, and GT0CON to control the GT2CON Gate 2 Connection:...
Page 87: Asynchronous Serial I/O Configuration
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 5.2.4 Asynchronous Serial I/O Configuration Figures 5-8 and 5-9 show the asynchronous serial I/O unit configuration, consisting of channels SIO0 and SIO1. Each channel has one output (SIOINT0, SIOINT1) to the interrupt control unit (see Figure 5-4) and two outputs to the DMA unit.
Page 88: Serial I/O Unit 0 Configuration
SIOCFG.0 SIO0 BCLKIN Receive Data SIOINT0 To ICU RBFDMA0 To DMA TXEDMA0 To DMA Transmit Data SIOCFG.6 Clear to Send Request to Send Data Set Ready Data Carrier Detect Data Terminal Ready Ring Indicator † Alternate pin signals are in parentheses. Figure 5-8.
Page 89: Serial I/O Unit 1 Configuration
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SIOCFG.1 SIO1 BCLKIN Receive Data SIOINT1 RBFDMA1 TXEDMA1 Transmit Data SIOCFG.7 Clear to Send Request to Send Data Set Ready Data Carrier Detect Data Terminal Ready Ring Indicator † Alternate pin signals are in parentheses. Figure 5-9.
Page 90: Sio And Ssio Configuration Register (Siocfg)
SIO and SSIO Configuration SIOCFG (read/write) — Number Mnemonic SIO1 Modem Signal Connections: 0 = Connects the SIO1 modem input signals to the package pins. 1 = Connects the SIO1 modem input signals internally. SIO0 Modem Signal Connections: 0 = Connects the SIO0 modem input signals to the package pins. 1 = Connects the SIO0 modem input signals internally.
Page 91: Synchronous Serial I/O Configuration
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 5.2.5 Synchronous Serial I/O Configuration The synchronous serial I/O unit (SSIO) is shown in Figure 5-11. Its single configuration register bit is in the SIOCFG register (Figure 5-10). The transmit buffer empty and receive buffer full sig- nals (SSTBE and SSRBF) go to the DMA unit (Figure 5-2), and an interrupt signal (SSIOINT) goes to the ICU (Figure 5-4).
Page 92: Chip-Select Unit And Clock And Power Management Unit Configuration
DEVICE CONFIGURATION 5.2.6 Chip-select Unit and Clock and Power Management Unit Configuration Figure 5-12 shows the multiplexing of signals of the Chip-select Unit and the Clock and Power Management Unit. The Chip-select signals, CS6# and CS5# are multiplexed with the REFRESH# signal from the Refresh Control Unit and the DACK0# signal from the DMA Unit, respectively.
Page 93: Configuration Of Chip-Select Unit And Clock And Power Management Unit
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CS0# CS1# CS2# CS3# CS4# CS5# CS6# Clock and Power Management Unit PWRDOWN Figure 5-12. Configuration of Chip-select Unit and Clock and Power Management Unit 5-20 P2CFG.0 To/From I/O Port 2 P2CFG.1 To/From I/O Port 2 P2CFG.2 To/From I/O Port 2 P2CFG.3...
Page 94: Core Configuration
5.2.7 Core Configuration Three coprocessor signals (ERROR#, PEREQ, and BUSY# in Figure 5-13) can be routed to the core, as determined by bit 5 of the PINCFG register (see Figure 5-15). Due to signal multiplexing at the pins, the coprocessor and Timer/counter2 cannot be used simultaneously. Core ERROR# PEREQ...
Page 95: Port 92 Configuration Register (Port92)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Setting bit 0 in the PORT92 register (see Figure 5-14) resets the core without resetting the periph- erals. Unlike the RESET pin, which is asynchronous and can be used to synchronize internal clocks to CLK2, this core-only reset is synchronized with the on-chip clocks and does not affect the on-chip clock synchronization.
Page 96: Pin Configuration
PIN CONFIGURATION Most of the microprocessor’s package pins support two peripheral functions. Some of these pins are routed to two peripheral inputs without the use of a multiplexer. These input-signal pairs are listed in Table 5-3. The pin is connected to both peripheral inputs. The remaining pins supporting two signals have multiplexers.
Page 97: Pin Configuration Register (Pincfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin. Pin Mode: 0 = Selects the coprocessor signals, PEREQ, BUSY#, and ERROR#, at 1 = Selects the timer control unit signals, TMROUT2, TMRCLK2, and...
Page 98: Port 1 Configuration Register (P1Cfg)
Port 1 Configuration P1CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P1.7 at the package pin. 1 = Selects HLDA at the package pin. Pin Mode: 0 = Selects P1.6 at the package pin. 1 = Selects HOLD at the package pin. Pin Mode: 0 = Selects P1.5 at the package pin.
Page 99: Port 2 Configuration Register (P2Cfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Port 2 Configuration P2CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. Pin Mode: 0 = Selects P2.6 at the package pin. 1 = Selects TXD0 at the package pin.
Page 100: Port 3 Configuration Register (P3Cfg)
Port 3 Configuration P3CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P3.7 at the package pin. 1 = Selects COMCLK at the package pin. Pin Mode: 0 = Selects P3.6 at the package pin. 1 = Selects PWRDOWN at the package pin. Pin Mode: 0 = Selects P3.5 at the package pin.
Page 101: Device Configuration Procedure
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DEVICE CONFIGURATION PROCEDURE Before configuring the microprocessor, make the following selections: • The set of peripherals to be used • The signals to be available at the package pins • The desired peripheral-peripheral and peripheral-core connections Although final decisions regarding these selections may be influenced by the possible configura- tions, we recommend that you initially make the selections without regard to limitations on the configurations.
Page 102: Example Design Solution
— Counter 2: Clock input is on-chip programmable clock (PSCLK); no signals connected to package pins • DMA Unit: — Not Used • Asynchronous Serial I/O channel 0 (SIO0): — Clock input is the internal clock SERCLK — RXD0, TXD0 connected to package pins —...
Page 103: Example Pin Configuration Registers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # P1CFG Value 0 = P1.7 1 = HLDA 0 = P1.6 1 = HOLD 0 = P1.5 1 = LOCK# 0 = P1.4 1 = RIO# 0 = P1.3 1 = DSR0# 0 = P1.2 1 = DTR0# 0 = P1.1...
Page 104: Example Dmacfg Configuration Register
Bit # 0 = Enables DACK1# at chip pin 1 = Disables DACK1# at chip pin 6–4 000 = DRQ1 pin (external peripheral) connected to DREQ1 001 = SIO channel 1’s receive buffer full signal (RBFDMA1) connected to DREQ1 010 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) to DREQ1 011 =SSIO receive holding buffer full signal (SSRBF) to DREQ1 100 = TCU counter 2’s output signal (OUT2) to DREQ1 101 = SIO channel 0’s receive buffer full signal (RBFDMA0) to DREQ1...
Page 105: Example Tmrcfg Configuration Register
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # 0 = All clock inputs enabled 1 = CLK2, CLK1, CLK0 forced to 0 0 = Connects GATE n to either the V 1 = Turns GATEn on or off, depending on whether bits 1, 3, and 5 are set or clear 0 = With bit 6 clear: V 1 = With bit 6 clear: TMRGATE2 pin conn.
Page 106: Example Intcfg Configuration Register
Bit # 0 = CAS2:0 disabled to pins 1 = CAS2:0 enabled from pins 0 = SIOINT1 connected to master IR3 1 = P3.1 connected to IR3 0 = SIOINT0 connected to master IR4 1 = P3.0 connected to IR4 0 = DMAINT connected to slave IR4.
Page 107: Pin Configuration Register Design Woksheet
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # P1CFG Value 0 = P1.7 1 = HLDA 0 = P1.6 1 = HOLD 0 = P1.5 1 = LOCK# 0 = P1.4 1 = RIO# 0 = P1.3 1 = DSR0# 0 = P1.2 1 = DTR0# 0 = P1.1...
Page 108: Dmacfg Register Design Worksheet
Bit # 0 = Enables DACK1# at chip pin 1 = Disables DACK1# at chip pin 6–4 000 = DRQ1 pin (external peripheral) connected to DREQ1 001 = SIO channel 1’s receive buffer full signal (RBFDMA1) connected to DREQ1 010 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) to DREQ1 011 =SSIO receive holding buffer full signal (SSRBF) to DREQ1 100 = TCU counter 2’s output signal (OUT2) to DREQ1 101 = SIO channel 0’s receive buffer full signal (RBFDMA0) to DREQ1...
Page 109: Tmrcfg Register Design Worksheet
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Bit # 0 = All clock inputs enabled 1 = CLK2, CLK1, CLK0 forced to 0 0 = Connects GATE n to either the V 1 = Turns GATEn on or off, depending on whether bits 1, 3, and 5 are set or clear. 0 = With bit 6 clear: V 1 = With bit 6 clear: TMRGATE2 pin conn.
Page 110: Intcfg Register Design Worksheet
Bit # 0 = CAS2:0 disabled to pins 1 = CAS2:0 enabled from pins 0 = SIOINT1 connected to master IR3 1 = P3.1 connected to IR3 0 = SIOINT0 connected to master IR4 1 = P3.0 connected to IR4 0 = DMAINT connected to slave IR4.
Page 112: Bus Interface Unit
BUS INTERFACE UNIT...
Page 114: Overview
The processor communicates with memory, I/O, and other devices through bus operations. Ad- dress, data, status, and control information define a bus cycle. The Bus Interface Unit supports read and write cycles to external memory and I/O devices. It also contains the signals that allow external bus masters to request and acquire control of the bus.
Page 115 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • Data status pins indicate that data is available on the data bus for a write (WR#) or that the processor is ready to accept data for a read (RD#). These pins are available so that certain system configurations can easily connect the processor directly to memory or I/O without external logic.
Page 116: Bus Signal Descriptions
6.1.1 Bus Signal Descriptions Table 6-1 describes the signals associated with the BIU. Table 6-1. Bus Interface Unit Signals (Sheet 1 of 2) Device Pin or Signal Internal Signal only A25:1 Device pins ADS# Device pin BHE# Device pins BLE# BS8# Device pin D15:0...
Page 117 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 6-1. Bus Interface Unit Signals (Sheet 2 of 2) Device Pin or Signal Internal Signal only M/IO# Device pins D/C# W/R# REFRESH# Device pin Device pin READY# Device pin Device pin Description Bus Cycle Definition Signals (Memory/IO, Data/Control, Write/Read, and Refresh): These four status outputs define the current bus cycle type, as shown in Table 6-2.
Page 118: Bus Operation
BUS OPERATION The processor generates eight different types of bus operations: • Memory data read (data fetch) • Memory data write • Memory code read (instruction fetch) • I/O data read (data fetch) • I/O data write • Halt or shutdown •...
Page 119: Basic External Bus Cycles
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Cycle 1 Nonpipelined External (Write) [Late Ready] State CLK2 CLKOUT A25:1, BHE# BLE#, D/C# Valid 1 M/IO# REFRESH# W/R# ADS# READY# LBA# BS8# LOCK# Valid 1 D15:0 Figure 6-1. Basic External Bus Cycles Cycle 2 Idle Cycle 3 Nonpipelined...
Page 120: Bus States
6.2.1 Bus States The processor uses a double-frequency clock input (CLK2). This clock is internally divided by two and synchronized to the falling edge of RESET (see Figure 8-2 in Chapter 8) to generate the internal processor clock signal. Each processor clock cycle is two CLK2 cycles wide. Each bus cycle is composed of at least two bus states: T1 and T2.
Page 121: Pipelining
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Memory read and memory write cycles can be locked to prevent another bus master from using the local bus. This allows for indivisible read-modify-write operations. Reset Asserted No Request Bus States: T1 - First clock of a non-pipelined bus cycle (CPU drives new address and asserts ADS#).
Page 122: Data Bus Transfers And Operand Alignment
Pipelining is also supported during memory cycles initiated by the two integrated DMA units. Refer to “Pipelined Cycle” on page 6-19 for a description of pipelined cycles. 6.2.3 Data Bus Transfers and Operand Alignment The processor can address up to 64 Mbytes (2 physical memory and up to 64 Kbytes (2 maintains separate physical memory and I/O spaces.
Page 123: Ready Logic
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • A doubleword (32-bit) transfer at (byte) address 03H requires three transfers, one word transfer and two byte transfers: — The first word transfer activates word address 04H and uses D15:0 (to write or read the middle 2 bytes of the 32-bit doubleword) —...
Page 124: Ready Logic
Unit To Internal Units When an internal cycle occurs, the LBA# signal becomes active in Phase 1 of the first T2 state. It then stays active until the rising edge of PH1 of the first T2, T2i or T2P state of the next bus cycle that requires external READY# to terminate the bus cycle.
Page 125: Basic Internal And External Bus Cycles
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Figure 6-4 shows internal and external bus cycles. Idle Cycle 1 Cycle Nonpipelined External (Write) [Late Ready] State CLK2 CLKOUT A25:1, BHE# BLE#, D/C# Valid 1 M/IO# REFRESH# W/R# ADS# READY# LBA# BS8# LOCK# Valid 1 D15:0 Figure 6-4.
Page 126: Bus Cycles
BUS CYCLES The processor executes five types of bus cycles: • Read • Write • Interrupt • Halt/shutdown • Refresh 6.3.1 Read Cycle Read cycles are of two types: • In a pipelined cycle, the address and status signals are output in the previous bus cycle, to allow longer memory access times.
Page 127 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL When a chip-select region is enabled for the current read cycle but internal READY# generation is disabled for that region, and the Chip-select Unit is programmed to insert wait-states, the READY# signal is ignored (not sampled) by the processor until the programmed number of wait-states are inserted into the cycle.
Page 128: Nonpipelined Address Read Cycles
Idle Cycle 1 Non-pipelined External (Read) CLK2 CLKOUT BHE#, BLE#, A25:1 Valid1 M/IO#, D/C# REFRESH# W/R# ADS# READY# LBA# BS8# LOCK# Valid1 D15:0 Figure 6-5. Nonpipelined Address Read Cycles BUS INTERFACE UNIT Cycle 2 Idle Non-pipelined External (Read) Valid2 End Cycle End Cycle Valid2 A2487-03...
Page 129: Write Cycle
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.3.2 Write Cycle Write cycles are of two types: • Pipelined. Pipelined write cycles are described in “Pipelined Cycle” on page 6-19. • Nonpipelined. Figure 6-6 shows two nonpipelined write cycles (one with and one without a wait state).
Page 130 The WR# signal can be deasserted in two ways. • Early Ready: WR# is deasserted at the rising edge of CLK2 in the middle of the T2 state, after any wait states programmed in the Chip-select Unit have expired. At the rising edge of PH2, READY# is sampled. If it is found active, WR# is synchronously deasserted in the middle of T2, driven inactive by the rising edge of the PH2 clock.
Page 131: Nonpipelined Address Write Cycles
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CLK2 CLKOUT BHE#, BLE#, A25:1 M/IO#, D/C# REFRESH# W/R# ADS# READY# LBA# BS8# LOCK# D15:0 Figure 6-6. Nonpipelined Address Write Cycles 6-18 Idle Cycle 1 Cycle 2 Nonpipelined Nonpipelined External External (Write) (Write) [Late Ready] [Early Ready] Valid1 Valid2...
Page 132: Pipelined Cycle
6.3.3 Pipelined Cycle The pipelining feature of the processor is normally used to achieve zero-wait-state memory sub- systems using devices that are slower than those in a zero-wait-state non-pipelined system. Pipe- lining allows bus cycles to be overlapped, increasing the amount of time available for the memory or I/O device to respond.
Page 133: Complete Bus States (Including Pipelined Address)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Reset Asserted Request Pending • HOLD Negated Bus States: T1—first clock of a non-pipelined bus cycle. T2—subsequent clock of a bus cycle when NA# has not been sampled active in the current bus cycle. T2i—subsequent clocks of a bus cycle when NA# has been sampled active in the current bus cycle and there is not yet an internal bus request pending.
Page 134: Pipelined Address Cycles
Cycle 1 Pipelined (Write) [Late Ready] CLK2 CLKOUT BHE#, BLE#, A25:1, Valid1 M/IO#, D/C# W/R# ADS# Note ADS# is asserted in every T2P state. Asserting NA# more than once during any cycle has no additional effects READY# LBA# BS8# LOCK# Valid 1 Out 1 D15:0...
Page 135 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL In cycle 3, NA# is sampled in the first T-state (T1P); the address and status have been valid for one previous T-state and this is a new bus cycle. NA# is sampled active and — because a bus cy- cle (cycle 4) is pending internally —...
Page 136: Interrupt Acknowledge Cycle
A complete discussion of the considerations for using pipelining can be found in the Intel386 SX Processor datasheet (order number 240187) or the Intel386™ SX Microprocessor Hardware Reference Manual (order number 240332). 6.3.4 Interrupt Acknowledge Cycle An interrupt causes the processor to suspend execution of the current program and execute in- structions from another program called an interrupt service routine.
Page 137 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Since the CAS lines are invalid in the Ti states between the two interrupt acknowledge cycles, cascading of external 82C59A devices requires latching the CAS lines. This ensures that the CAS lines remain valid during these Ti states to fulfill the requirements of the external 82C59A devices.
Page 138: Interrupt Acknowledge Cycles
BUS INTERFACE UNIT Previous Interrupt Idle Interrupt Idle Acknowledge Acknowledge Cycle (Four bus states) Cycle 1 Cycle 2 (Internal) (Internal) CLK2 CLKOUT BHE# BLE#, A25:A3, A1 M/IO#, D/C#, W/R# ADS# READY# LBA# LOCK# A2490-03 Figure 6-9. Interrupt Acknowledge Cycles 6-25...
Page 139: Halt/Shutdown Cycle
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.3.5 Halt/Shutdown Cycle The halt condition occurs in response to a HALT instruction. The shutdown condition occurs when the processor is processing a double fault and encounters a protection fault; the processor cannot recover and therefore, shuts down. Externally, a shutdown cycle differs from a halt cycle only in the resulting address bus outputs.
Page 140: Halt Cycle
Cycle 1 Nonpipelined (Write) [Late Ready] CLK2 CLKOUT BHE#, A1, M/IO#, W/R# Valid 1 A25:2, BLE#, D/C# Valid 1 ADS# READY# LBA# Valid 1 LOCK# D15:0 HALT cycle must be acknowledged by READY# asserted. This READY# could be † generated internally or externally. Figure 6-10.
Page 141: Refresh Cycle
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.3.6 Refresh Cycle The refresh control unit simplifies dynamic memory controller design by issuing dummy read cy- cles at specified intervals. (For more information, refer to Chapter 15, “REFRESH CONTROL UNIT.”) Figure 6-11 shows a basic refresh cycle. The sequence of signals for a refresh cycle is as follows: Like a read cycle, the refresh cycle is initiated by asserting ADS# and completed by asserting READY#.
Page 142: Basic Refresh Cycle
Idle Cycle 1 Nonpipelined External (Read) CLK2 CLKOUT BHE#, BLE# Valid 1 M/IO#, D/C# Valid 1 A25:1 REFRESH# W/R# ADS# READY# LBA# Valid 1 LOCK# D15:0 HOLD HLDA Figure 6-11. Basic Refresh Cycle BUS INTERFACE UNIT Idle Cycle 2 Idle Refresh Valid 2 Float...
Page 143: Refresh Cycle During Hold/Hlda
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Idle CLK2 CLKOUT BHE#, BLE# M/IO#, D/C# REFRESH# A25:1 W/R# ADS# READY# LBA# LOCK# D15:0 HOLD HLDA Figure 6-12. Refresh Cycle During HOLD/HLDA 6-30 HOLD Idle Cycle 1 Acknowledge Refresh Floating Floating Valid 1 Floating Floating Floating...
Page 144: Bs8 Cycle
6.3.7 BS8 Cycle The BS8 cycle allows external logic to dynamically switch between an 8-bit data bus size and a 16-bit data bus size, by using the BS8# signal. Figure 6-13 shows a word access to an 8-bit pe- ripheral. To use the dynamic 8-bit bus sizing, an external memory or I/O should connect to the lower eight bits of the data bus (D7:0), use the BLE# as address bit 0, and assert BS8# (at the BS8# pin) in T2 of a memory or I/O access.
Page 145 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The BS8 cycle generates additional bus cycles for read and write cycles only. For interrupt and halt/shutdown cycles, the accesses are byte wide and the BS8# signal is ignored. For a refresh cycle, the byte enables are both disabled and the BS8# signal is ignored. If a BS8 cycle requires an additional bus cycle, the processor retains the current address for the second cycle.
Page 146: Bit Cycles To 8-Bit Devices (Using Bs8#)
Low Byte High Byte Write Write [Late Ready] [Late Ready] State CLK2 CLKOUT A25:1 Valid 1 M/IO# D/C# BLE# BHE# W/R# ADS# Must be high READY# BS8# Valid 1 LOCK# Data Out High D15:8 Data Out D7:0 Figure 6-13. 16-bit Cycles to 8-bit Devices (Using BS8#) BUS INTERFACE UNIT Low Byte High Byte...
Page 147: Bus Lock
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL BUS LOCK In a system in which more than one device (a bus master) may control the local bus, locked cycles are used to make sequential bus cycles indivisible. Otherwise, the cycles may be separated by a cycle from another bus master.
Page 148: Lock# Signal Duration
BUS INTERFACE UNIT Unlocked Locked Locked Unlocked Bus Cycle Bus Cycle Bus Cycle Bus Cycle CLKOUT Address Asserted BLE#, BHE#, A25:1 LOCK Deasserted LOCK# READY# A2489-02 Figure 6-14. LOCK# Signal During Address Pipelining 6.4.3 LOCK# Signal Duration The maximum duration of the LOCK# signal affects the maximum HOLD request latency be- cause HOLD is recognized only after LOCK# goes inactive.
Page 149: Hold/Hlda Timing
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.5.1 HOLD/HLDA Timing To gain control of the local bus, the requesting bus master drives the HOLD input active. This signal can be asynchronous to the processor’s CLK2 input. The processor responds by: • completing its current bus cycle •...
Page 150: Hold Signal Latency
• NMI pin - The request is recognized and latched. It is serviced after HOLD is released. • SMI# pin - The request is recognized and latched. It is serviced after HOLD is released. 6.5.2 HOLD Signal Latency Because other bus masters may be used in time-critical applications, the amount of time the bus master must wait for bus access (HOLD latency) can be a critical design consideration.
Page 151: Design Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DESIGN CONSIDERATIONS • Upon reset, UCS# is configured as a 16-bit chip-select signal. If the Boot device is only an 8-bit device, then BS8# must be asserted whenever UCS# is active (until the UCS region can be reprogrammed to reflect an 8-bit region).
Page 152: System Configuration
6.6.1.1 System Configuration The Intel387 SX Math Coprocessor can be interfaced to the Intel386 EX embedded processor as shown in Figure 6-15. W/R# ADS# M/IO# CLK2 RESET BUSY# PEREQ ERROR# READY# D15:0 LBA# Intel386™ EX 80386EX Embedded Processor Figure 6-15. Intel386 EX Processor to Intel387 SX Math Coprocessor Interface A dedicated communication protocol makes possible high-speed transfer of opcodes and oper- ands between the Intel386 EX processor and the Intel387 SX math coprocessor.
Page 153: Software Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The interface has these characteristics: • The Intel387 SX Math Coprocessor shares the local bus of the Intel386 EX processor. • The Intel386 EX processor and Intel387 SX Math Coprocessor share the same reset signals. They also share the same clock input.
Page 154: Intel386 Ex Processor To Sram/Flash Interface
Also, bit 5 in the PINCFG register (Figure 5-15 on page 5-24) must be cleared, to connect the coprocessor-related signals of the core to the package pins. Below is an example of a simple routine that can be executed using the math-coprocessor: fninit fldpi fld1...
Page 155: Intel386 Ex Processor To Psram Interface
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.6.3 PSRAM Interface Pseudo SRAM (PSRAM) devices can be easily interfaced (Figure 6-17) to the Intel386 EX pro- cessor. PSRAM devices have an interface that is similar to SRAM devices (They are also pin- compatible in many cases).
Page 156: Intel386 Ex Processor To Paged Dram Interface
6.6.4 Paged DRAM Interface External logic is required to interface the Intel386 EX processor to DRAM devices, as shown in Figure 6-18. The PLD generates the RAS# and CAS# signals. If RAS#-Only Refresh is being performed (using the Refresh Control Unit of the processor), then during a Refresh Cycle, the PLD enables the Column Address Buffer and asserts the RAS# signal (shaded sections in the figure).
Page 157: Intel386 Ex Processor And Non-Paged Dram Interface
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 6.6.5 Non-Paged DRAM Interface This interface is similar to the Paged DRAM Interface, except that in this case, the lower address bits are routed to the Row Address Buffer and the higher address bits to the Column Address Buffer.
Page 158: System Management Mode
SYSTEM MANAGEMENT MODE...
Page 160: System Management Mode Overview
The Intel386™ EX processor provides a mechanism for system management with a combination of hardware and CPU microcode enhancements. For low power systems, the primary function of SMM is to provide a transparent means for power management. For systems where power man- agement is not critical, SMM may be used for other functions such as alternate operating systems, debuggers, hard disk drive backup, or virtual I/O.
Page 161: Smm Active Output (Smiact#)
These requirements are made to ensure that the SMM remains transparent to non-SMM code and to maintain uniformity across the various Intel processors that support this mode. It is possible for the designer of an embedded system to place the SMM driver code in read-only storage, as long as the address space between 03FE00H and 03FFFFH is writable.
Page 162: System Management Mode Programming And Configuration
ports the relocation of SMRAM. When this bit is set (1), the processor supports SMRAM reloca- tion. When this bit is cleared (0), then the processor does not support SMRAM relocation. Since this device doesn’t support SMRAM relocation, bit 17 of the SMM Revision Identifier is cleared. The SMRAM address space is fixed from 38000H to 3FFFFH.
Page 163: System Management Interrupt
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL is no 64 Kbyte limit. The value loaded into the selector register is shifted to the left four bits and moved into its corresponding descriptor base, then added to the effective address. The effective address can be generated indirectly, using a 32-bit register.
Page 164: Standard Smi#
of the CPU is saved to the SMM State Dump Area. After executing a RSM instruction, the CPU proceeds to the next application code instruction (see instruction #4 in Figure 7-1). SMM latency is measured from the falling edge of SMI# to the first ADS# where SMIACT# is active (see Fig- ure 7-2).
Page 165: Smiact# Latency
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CLK2 T1 T2 CLKOUT SMI# ADS# READY# SMIACT# Normal State A = 1 CLK min, B = 20 CLK min, C = 16 CLK min, D = 4 CLK min Even if bus cycles are pipelined, the minimum clock numbers are guaranteed. State Save, SMM Handler, State Restore Figure 7-2.
Page 166: Smi# Priority
7.3.2.1 SMI# Priority When more than one exception or interrupt is pending at an instruction boundary, the processor services them in a predictable order. The priority among classes of exception and interrupt sourc- es is shown in Table 7-3. The processor first services a pending exception or interrupt from the class that has the highest priority, transferring execution to the first instruction of the handler.
Page 167: System Management Interrupt During Halt Cycle
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 7.3.2.2 System Management Interrupt During HALT Cycle Since SMI# is an asynchronous signal, it may be generated at any time. A condition of interest arises when an SMI# occurs while the CPU is in a HALT state. To give the system designer max- imum flexibility, the processor allows an SMI# to optionally exit the HALT state.
Page 168: Halt Restart
7.3.2.3 HALT Restart It is possible for SMI# to break into the HALT state. In some cases the application might want to return to the HALT state after RSM. The SMM architecture provides the option of restarting the HALT instruction after RSM. The word at address 03FF02H is the HALT restart slot.
Page 169: I/O Restart
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CLK2 SMI# T su RDY# T su = SMI# setup time, T hold = SMI# hold time 7.3.2.5 I/O Restart Bit 16 of the SMM Revision Identifier is set (1) indicating that this device does support the I/O trap restart extension to the SMM base architecture.
Page 170: Halt During Smm Handler
SYSTEM MANAGEMENT MODE then any pending INTR and NMI is serviced after completion of RSM instruction execution. Only one INTR and one NMI can be pending. The SMM handler may choose to enable interrupts to take advantage of device drivers. Since in- terrupts were enabled while under control of the SMM handler, the signal SMIACT# continues to be asserted.
Page 171: Halt During Smm Handler
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SMI# Instr Instr State Save Handler INTR & NMI Figure 7-7. HALT During SMM Handler 7.3.3.3 Idle Mode and Powerdown Mode During SMM Both Idle Mode and Powerdown Mode may be used while in SMM. Entering and exiting either of these power management modes from SMM is identical to entering or exiting from normal mode.
Page 172 exactly as if they represented another address line. The following options are supported by the chip select unit: CASMM To see how this extension of the CSU supports the SMRAM requirements, consider an embedded system which has 1 Mbyte of 16-bit wide EPROM in the region 03F00000H to 03FFFFFFH and 1 Mbyte of 16-bit wide RAM in the region 00000000H to 000FFFFFH.
Page 173: Smram State Dump Area
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 7.3.4.2 SMRAM State Dump Area The SMM State Save sequence asserts SMIACT#. This mechanism indicates to internal modules that the CPU has entered and is currently executing SMM. The resume (RSM) instruction is only valid when in SMM.
Page 174: Resume Instruction (Rsm)
SYSTEM MANAGEMENT MODE The programmer should not modify the contents of this area in SMRAM space directly. SMRAM space is reserved for CPU access only and is intended to be used only when the processor is in SMM. 7.3.5 Resume Instruction (RSM) After an SMI# request is serviced, the RSM instruction must be executed to allow the CPU to return to an application transparently after servicing the SMI#.
Page 175: Programming Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL PROGRAMMING CONSIDERATIONS 7.5.1 System Management Mode Code Example The following code example contains these software routines. SerialWriteStr2 Located in SMRAM upon program execution, this routine loops endlessly while writing a character “X” out the serial port on the EV386EX board.
Page 176 ---------------------------------------------------------------------------*/ void SerialWriteStr2() /* Loops while writing a char out to the serial port */ _asm ax,0x3900 ss,ax mov sp,0x100 Forever: dx,0xf4fd TstStatus: al,dx testal,0x20 TstStatus // Code below is same as _SetEXRegByte(TransmitPortAddr,’X’) ax,’X’ dx,0xf4f8 dx, al Forever /*********************** Function SerialWriteStr ************************** Parameters: Unit Unit number of the serial port.
Page 177 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /*************************** Function InitSIO ******************************* Parameters: Unit Unit number of the serial port. port 1. Mode Defines parity, number of data bits, number of stop bits... Reference Serial Line Control register for various options ModemCntrl Defines the operation of the modem control lines BaudRate Specifies baud rate.
Page 178 _SetEXRegByte(SIOPortBase + DLH, HIBYTE(BaudDivisor) ); _SetEXRegByte(SIOPortBase + DLL, LOBYTE(BaudDivisor) ); // Set Serial Line control register _SetEXRegByte(SIOPortBase + LCR, Mode); // Sets Mode and resets the // Set modem control bits _SetEXRegByte(SIOPortBase + MCR, ModemCntrl); return E_OK; /******************************* MAIN ***********************************/ Parameters: None Returns:...
Page 179 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SetEXRegWordInline(CS2ADL,0x08700); SetEXRegWordInline(CS2ADH,0x3); SetEXRegWordInline(CS2MSKL,0x07C01); SetEXRegWordInline(CS2MSKH,0x00); _asm mov ax,0x3800 mov es,ax mov ax,seg SerialWriteStr2 mov ds,ax mov cx,0x100 mov si,offset SerialWriteStr2 mov di,0 rep movsb SetEXRegWordInline(CS2MSKL,0x7801); // Resets SRAM to enabled in SMM only _asm pop DI pop SI pop DS pop ES...
Page 180: Clock And Power Management Unit
CLOCK AND POWER MANAGEMENT UNIT...
Page 182: Overview
CLOCK AND POWER MANAGEMENT UNIT The clock generation circuitry provides uniform, nonoverlapping clock signals to the core and in- tegrated peripherals. The power management features control the clock signals to provide power conservation options. This chapter is organized as follows: •...
Page 183: Clock And Power Management Unit Connections
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Three of the internal peripherals have selectable clock sources. • The asynchronous serial I/O (SIO) unit can use either the SERCLK signal or an external clock (connected to the COMCLK pin) as its clock source. •...
Page 184: Power Management Logic
The signal from the RESET pin is also routed to the clock generation unit, which synchronizes the processor clock with the falling edge of the RESET signal and provides a synchronous inter- nal RESET signal to the rest of the device. The RESET falling edge can occur in either PH1 or PH2.
Page 185: Smm Interaction With Power Management Modes
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL vice enters the programmed mode when the HALT cycle is terminated by a valid READY#. This READY# may be generated either internally or externally. A device reset, an NMI or SMI#, or any unmasked interrupt request from the interrupt control unit causes the device to exit the power management mode.
Page 186: Bus Interface Unit Operation During Idle Mode
Halt Instruction with Powerdown Flag Set Powerdown Mode RSM with Powerdown Flag and Halt Restart Slot Set Reset or RSM Instruction with Halt Restart Slot Clear Figure 8-3. SMM Interaction with Idle and Powerdown Modes 8.1.2.2 Bus Interface Unit Operation During Idle Mode The bus interface unit (BIU) can process DMA, DRAM refresh, and external hold requests during idle mode.
Page 187: Clock And Power Management Signals
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 8.1.3 Clock and Power Management Registers and Signals Table 8-1 lists the registers and Table 8-2 list the signals associated with the clock and power man- agement unit. Table 8-1. Clock and Power Management Registers Expanded Register Address...
Page 188: Clock Prescale Register (Clkprs)
CONTROLLING THE PSCLK FREQUENCY The PSCLK signal can provide a 50% duty cycle prescaled clock to the timer/counter and SSIO units. This feature is useful for providing various frequencies, including a 1.19318 MHz output for a PC-compatible system timer, or speaker tone generator. Determine the required prescale val- ue using the following formula, then write this value to the CLKPRS register (Figure 8-4).
Page 189: Power Control Register (Pwrcon)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CONTROLLING POWER MANAGEMENT MODES Two power management modes are available: idle and powerdown. These modes are clock dis- tribution functions controlled by the power control register (PWRCON), shown in Figure 8-5. Power Control Register PWRCON (read/write) —...
Page 190: Timing Diagram, Entering And Leaving Idle Mode
8.3.1 Idle Mode Idle mode freezes the core clocks (PH1C low and PH2C) high, and leaves the peripheral clocks (PH1P and PH2P) toggling. To enter idle mode: Program the PWRCON register (Figure 8-5). Execute a HALT instruction. The CPU enters idle mode when READY# terminates the halt bus cycle. CLKOUT continues to run while the CPU is in idle mode.
Page 191: Powerdown Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 8.3.2 Powerdown Mode Powerdown mode freezes both the core clocks and the peripheral clocks (PH1C and PH1P low, PH2C and PH2P high). The BIU cannot acknowledge DMA, refresh, and external hold requests in powerdown mode, since all the clocks are frozen. To enter powerdown mode, follow these steps: Program the PWRCON register (Figure 8-5).
Page 192: Design Considerations
CLK2 CLKOUT/PH1P/PH1C PH2P/PH2C PWRDOWN CLK2 CLKOUT/PH1P/PH1C PH2P/PH2C PWRDOWN Figure 8-7. Timing Diagram, Entering and Leaving Powerdown Mode DESIGN CONSIDERATIONS This section outlines design considerations for the clock and power management unit. 8.4.1 Reset Considerations External circuitry must provide an input to the RESET pin. The RESET input must remain high for at least 16 CLK2 cycles to reset the chip properly.
Page 193: Power-Up Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Asynchronous RESET CLK2 Figure 8-8. Reset Synchronization Circuit 8.4.2 Power-up Considerations 8.4.2.1 Built-in Self Test The Intel386 EX processor supports the Intel386 SX processor built-in self-test (BIST) mode for testing core functions. To initiate the self test, follow these steps: Hold the RESET pin high for a minimum of 80 CLK2 cycles.
Page 194: Powerdown Mode And Idle Mode Considerations
8.4.3 Powerdown Mode and Idle Mode Considerations • The “wake-up” signals (INT, NMI, and SMI#) are level-sensitive inputs to the wake-up circuitry. The active state of any of these inputs prevents the device from entering powerdown or idle mode. • The refresh control unit cannot perform DRAM refreshes during powerdown.
Page 195 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL None Syntax: int error; WORD psclk = 0x02; error = Set_Prescale_Value(psclk); Real/Protected Mode: No changes required. ******************************************************************************/ int Set_Prescale_Value(WORD Prescale) WORD clkprs = 0x0000; clkprs = _GetEXRegWord(CLKPRS); /* clear lowest nine bits of clkprs */ clkprs = clkprs &...
Page 196 No changes required. ******************************************************************************/ void Enter_Idle_Mode(void) BYTE pwrcon = 0x00; pwrcon = _GetEXRegByte(PWRCON); /* clear lowest two bits of pwrcon */ pwrcon = pwrcon & 0xfc; /* Set mode to idle */ _SetEXRegByte(PWRCON, (pwrcon | IDLE)); /* call HALT instruction to execute IDLE mode */ _asm { }/* Enter_Idle_Mode */ /*****************************************************************************...
Page 197 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* clear lowest two bits of pwrcon */ pwrcon = pwrcon & 0xfc; /* Set mode to powerdown */ _SetEXRegByte(PWRCON, pwrcon | PWDWN); /* call HALT instruction to execute POWERDOWN mode */ _asm { }/* Enter_Powerdown_Mode */ /***************************************************************************** Mode_Setting_To_Active:...
Page 198: Interrupt Control Unit
INTERRUPT CONTROL UNIT...
Page 200: Overview
The Interrupt Control Unit (ICU) consists of two cascaded interrupt controllers, a master and a slave, that allow internal peripherals and external devices (through interrupt pins) to interrupt the core through its interrupt input. The interrupt control unit is functionally identical to two industry-standard 82C59As connected in cascade.
Page 201 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The slave 82C59A is cascaded from (or connected to) the master’s IR2 signal. Like the master, the slave uses a programmable priority structure. When the slave receives an interrupt request, it sends the request to the master (assuming the request is enabled and has sufficient priority). The master sees the slave request as a request on its IR2 line.
Page 202: Interrupt Control Unit Configuration
8259A P3CFG.2 Master INTCFG.6 INTR core) INTCFG.5 P3CFG.3 P3CFG.4 CAS2:0 P3CFG.5 INTCFG.0 8259A INTCFG.1 Slave OUT2(TCU) INTCFG.4 CAS2:0 INTCFG.2 WDTOUT# † Alternate pin signals are in parentheses Heavier lines indicate multiple signals. Figure 9-1. Interrupt Control Unit Configuration INTERRUPT CONTROL UNIT OUT0 (TCU) To/From I/O Port 3 MCR1.3...
Page 203: Icu Operation
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL ICU OPERATION The following sections describe the ICU operation. The ICU’s interrupt sources, interrupt priority structure, interrupt vectors, interrupt processing, and polling mode are discussed. 9.2.1 Interrupt Sources The ICU support a total of 18 interrupt sources (see Table 9-1) but only a maximum of 15 simul- taneous sources.
Page 204: C59A Master And Slave Interrupt Sources
Table 9-1. 82C59A Master and Slave Interrupt Sources Master IR Source Line TMROUT0 (timer control unit) INT0 (device pin) Slave 82C59A Cascade SIOINT1 (SIO unit) INT8 (device pin) SIOINT0 (SIO unit) INT9 (device pin) INT1 (device pin) INT2 (device pin) INT3 (device pin) Connected...
Page 205: Interrupt Priority
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Interrupt processing begins with the assertion of an IR signal. During the ICU initialization pro- cess (described in “Register Definitions” on page 9-15), you can program the ICU to be either edge-triggered or level-triggered. See “Interrupt Detection” on page 9-29 for a description of the difference between level and edge triggered signals.
Page 206: Determining Priority
Default Highest Becomes Level Highest Level Specified Lowest Lowest Level Level Figure 9-2. Methods for Changing the Default Interrupt Structure 9.2.2.2 Determining Priority There are three modes that determine relative priorities, i.e., whether a level higher, lower, or equal to another level has higher or lower interrupt priority. Fully nested In the fully nested mode, higher level IR signals have higher interrupt priority.
Page 207: Interrupt Vectors
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL processing of a lower-level slave interrupt. The special fully nested mode is generally used by the master in a cascaded system. Special mask In some applications, you may want to allow lower-level requests interrupt the processing of higher-level interrupts. The special mask mode supports these applications.
Page 208: Interrupt Process
9.2.4 Interrupt Process Each IR signal has a mask, a pending, and an in-service bit associated with it. • The mask bit disables the IR signal. The respective mask bits provide a way to individually disable the IR signals. You can globally disable all interrupts to the core using the CLI instruction.
Page 209 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Unlike the AEOI mode (this is a mode, and not a command like specific EOI or nonspecific EOI), which is enabled during initialization, the other methods are commands issued during interrupt processing, usually at the end of an interrupt’s service routine.
Page 210: Interrupt Process – Master Request From Non-Slave Source
Master receives an interrupt request. (From a non-slave source.) Master sets the request's pending bit. special request mask mode enabled? enabled? in-service bit for this request set? Master sends request to CPU. CPU initiates interrupt acknowledge cycle. Master clears request's pending bit, sets its in-service bit, and puts its interrupt vector number on the bus.
Page 211: Interrupt Process – Slave Request
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL request enabled? Note: See the "Interrupt Process - Master Request from Slave Source" figure for the continuation of this flow chart. Figure 9-4. Interrupt Process – Slave Request 9-12 Slave receives an interrupt request. Slave sets the request's pending bit.
Page 212: Interrupt Process – Master Request From Slave Source
Master receives IR2 interrupt request. Master sets its IR2 pending bit. special request mask mode enabled? enabled? IR2 in-service set? Master sends request to CPU. CPU initiates interrupt acknowledge cycle. Master clears IR2 pending bit and sets IR2 in-service bit. Slave clears its pending bit, sets its in-service bit, and puts its interrupt vector number on the bus.
Page 213: Poll Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The interrupt’s priority structure determines which EOI command should be used. Use the spe- cific EOI command for the special mask mode. In this mode, a lower-level interrupt can interrupt the processing of a higher-level interrupt. The specific EOI command is necessary because it al- lows you to specifically clear the lower level in-service bit.
Page 214: Register Definitions
configuring more than six external 82C59As. Since the polling mode doesn’t require that the ad- ditional 82C59As be cascaded from the master, the number of interrupt request sources for a polled system is limited only by the number of 82C59As that the system can address. Polling and standard interrupt processing can be used within the same program.
Page 215: Icu Registers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 9-2. ICU Registers (Sheet 1 of 2) Expanded Register Address P3CFG 0F824H (read/write) INTCFG 0F832H (read/write) ICW1 (master) 0F020H ICW1 (slave) 0F0A0H (write only) ICW2 (master) 0F021H ICW2 (slave) 0F0A1H (write only) ICW3 (master) 0F021H (write only) ICW3 (slave)
Page 216 Table 9-2. ICU Registers (Sheet 2 of 2) Expanded Register Address IRR (master) 0F020H IRR (slave) 0F0A0H (read only) ISR (master) 0F020H ISR (slave) 0F0A0H (read only) POLL (master) 0F020H 0F021H POLL (slave) 0F0A0H 0F0A1H (read only) NOTE: All master 82C59A registers are accessed through two expanded or PC/AT addresses; all the slave registers are accessed through two other expanded or PC/AT addresses.
Page 217: Port 3 Configuration Register (P3Cfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.1 Port 3 Configuration Register (P3CFG) Use the P3CFG register to connect the interrupt request signals (INT3:0) to the package pins. These signals are multiplexed with port 3 signals, P3.5–2. Connecting a port 3 signal to the pack- age pin also connects V to the corresponding master’s IR signal, disabling the signal.
Page 218: Interrupt Configuration Register (Intcfg)
9.3.2 Interrupt Configuration Register (INTCFG) Use the INTCFG register to connect the INT9:4 interrupt request pins to the master’s and the slave’s IR signals and to enable the master’s external cascade signals. When enabled, the cascade signals appear on address lines A18:16 during interrupt acknowledge cycles. Every external slave monitors these lines to determine whether it is the slave being addressed.
Page 219: Initialization Command Word 1 Register (Icw1)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.3 Initialization Command Word 1 (ICW1) Initialization begins with writing ICW1. Use ICW1 to select the interrupt request triggering type (level or edge). The following actions occur within an 82C59A module when its ICW1 is written: •...
Page 220: Initialization Command Word 2 Register (Icw2)
9.3.4 Initialization Command Word 2 (ICW2) Use the ICW2 register to define the base interrupt vector for the 82C59A. Valid vector numbers for maskable interrupts range from 32 to 255. Because the base vector number must reside on an 8-byte boundary, the valid base vector numbers are 32 + n × 8 where 0 interrupt vector’s five most-significant bits to ICW2’s five most-significant bits.
Page 221: Initialization Command Word 3 Register (Icw3 – Master)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.5 Initialization Command Word 3 (ICW3) The ICW3 register contains information about the master/slave connections. For this reason, the functions of the master’s ICW3 and the slave’s ICW3 differ. ICW3 (at 0F021H or 0021H) is the master’s cascade configuration register (Figure 9-11). The master has an internal slave cascaded from its IR2 signal.
Page 222: Initialization Command Word 3 Register (Icw3 – Slave)
ICW3 (at 0F0A1H or 00A1H) is the internal slave ID register (Figure 9-11). Use this register to indicate that the slave is cascaded from the master’s IR2 signal. This gives the internal slave an ID of 2. Each slave device uses the IDs to determine whether it is the slave being addressed. Dur- ing a slave access, the slave’s ID is driven on the master’s CAS2:0 signals.
Page 223: Initialization Command Word 4 Register (Icw4)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.6 Initialization Command Word 4 (ICW4) Use ICW4 to select the special-fully nested mode or the fully nested mode and to enable the au- tomatic EOI mode. Initialization Command Word 4 ICW4 (master and slave) (write only) Number Mnemonic...
Page 224: Operation Command Word 1 (Ocw1)
9.3.7 Operation Command Word 1 (OCW1) OCW1 is the interrupt mask register. Setting a bit in the interrupt mask register disables (masks) interrupts from the corresponding IR signal. For example, setting the master’s OCW1 M3 bit dis- ables interrupts from the master IR3 signal. Clearing a bit in the interrupt mask register enables interrupts from the corresponding IR signal.
Page 225: Operation Command Word 2 (Ocw2)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.8 Operation Command Word 2 (OCW2) Use OCW2 to change the priority structure and issue EOI commands. Operation Command Word 2 OCW2 (master and slave) (write only) Number Mnemonic The Rotate (R), Specific Level (SL), and End-of-Interrupt (EOI) Bits: These bits change the priority structure and/or send an EOI command.
Page 226: Operation Command Word 3 (Ocw3)
9.3.9 Operation Command Word 3 (OCW3) Use OCW3 to enable the special mask mode, issue a poll command, and provide access to the interrupt in-service and request registers (ISR, IRR). Operation Command Word 3 OCW3 (master and slave) (write only) ESMM Number Mnemonic...
Page 227: Interrupt Request Register (Irr)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 9.3.10 Interrupt Request Register (IRR) This 8-bit, read-only register contains the levels requesting an interrupt to be acknowledged. It is accessed using OCW3 (see Figure 9-15). The highest request level is reset from the IRR when an interrupt is acknowledged.
Page 228: Design Considerations
DESIGN CONSIDERATIONS The following sections discuss some design considerations. 9.4.1 Interrupt Acknowledge Cycle When the core receives an interrupt request from the master, it completes the instruction in progress and any succeeding locked instructions, then initiates an interrupt acknowledge cycle. The interrupt acknowledge cycle generates an internal interrupt acknowledge (INTA#) signal that consists of two locked pulses (Figure 9-17).
Page 229: Spurious Interrupts
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Level triggered The 82C59A recognizes a high level on an IR line as an interrupt request. A device must maintain the high level until after the falling edge of the first INTA# pulse. Unlike an edge-triggered IR signal, a level- triggered IR signal continues to generate interrupts as long as it is asserted.
Page 230: Cascading External 82C59A Interrupt Controllers
Intel386™ EX Processor READY# READY# M/IO# W/R# D/C# ADS# LBA# CLKOUT CLK2 CAS0 CAS1 CAS2 Latch INT x INT y BLE# CS x # CS y # D7:0 Figure 9-19. Cascading External 82C59A Interrupt Controllers INTERRUPT CONTROL UNIT INTA# INTA# READY# State Machine...
Page 231: Programming Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL PROGRAMMING CONSIDERATIONS Consider the following when programming the ICU. • When an 82C59A receives an interrupt request, it sets the request’s pending bit (regardless of whether the IR signal is masked or not). The pending bit remains set until the interrupt is serviced.
Page 232 BYTE _CascadeBits_ = 0x4; /***************************************************************************** InitICU Description: Initialization for both the master and slave Interrupt Control Units (ICU). tine only initializes the internal interrupt controllers, external ICUs must be initialized separately. These should be initialized before interrupts are enabled(i.e., enable()). Parameters: MstrMode Mode of operation for Master ICU...
Page 233 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Real/Protected Mode No changes required. *****************************************************************************/ int InitICU(BYTE MstrMode, BYTE MstrBase, BYTE MstrCascade, BYTE SlaveMode, BYTE SlaveBase, BYTE MstrPins, BYTE SlavePins) BYTE icw, cfg_pins; /* Program Slave ICU */ _IRQ_SlaveBase_ = SlaveBase & 0xf8; _SetEXRegByte(ICW1S, 0x11 | SlaveMode);// Set slave triggering _SetEXRegByte(ICW2S, _IRQ_SlaveBase_);...
Page 234 /***************************************************************************** InitICUSlave Description: Initialization only the internal slave Interrupt Control Units (ICU). This routine only initializes the internal interrupt controller, external ICUs must be initialized separately. Parameters: SlaveMode Mode of operation for Slave ICU SlaveBase Specifies the base interrupt vector number for the Slave interrupts.
Page 235 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL _IRQ_SlaveBase_ = SlaveBase & 0xf8; _SetEXRegByte(ICW1S, 0x11 | SlaveMode); _SetEXRegByte(ICW2S, _IRQ_SlaveBase_); // Set slave base interrupt _SetEXRegByte(ICW3S, 0x2); _SetEXRegByte(ICW4S, 0x1); cfg_pins = _GetEXRegByte(INTCFG); cfg_pins |= SlavePins; _SetEXRegByte(INTCFG, SlavePins); return E_OK; }/* InitICUSlave */ /***************************************************************************** Disable8259Interrupt: Description: Disables 8259a interrupts for the master and the slave.
Page 236 #define IR7 Disable8259Interrupt(IR0 | IR1 | IR3 | IR4 | IR5 | IR6 | IR7, IR1 | IR2 | IR3 | IR4 |IR5 | IR6); Real/Protected Mode No changes required. *****************************************************************************/ void Disable8259Interrupt(BYTE MstrMask, BYTE SlaveMask) BYTE Mask; if(MstrMask != 0) Mask = _GetEXRegByte(OCW1M);...
Page 237 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* ICU IRQ Mask Values*/ #define IR0 #define IR1 #define IR2 #define IR3 #define IR4 #define IR5 #define IR6 #define IR7 Enable8259Interrupts(IR2, IR0 | IR7); //Enable MasterIR2 for cascading Real/Protected Mode No changes required. *****************************************************************************/ void Enable8259Interrupt(BYTE MstrMask, BYTE SlaveMask) BYTE Mask;...
Page 238 supports INTERRUPT_ISR (parameter is ignored). Protected mode supports both. Returns:Error Code E_INVALID_VECTOR -- An IRQ of greater than 15 was passed E_BADVECTOR -- IRQ is used for cascading to a slave interrupt controller E_OK -- Initialized OK, No error. Assumptions: Compiler supports far and interrupt keywords ICU must be configured before this function is call for it to operate properly...
Page 239 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL return E_OK; }/* SetIRQVector */ /***************************************************************************** SetInterruptVector: Description: Loads the interrupt vector table with the address of the interrupt routine. The vector table entry number is determined by the vector number. Parameters: InterProc Address of interrupt function, will be loaded into the interrupt table.
Page 240 Poll_Command: Description: This routine issues a poll command which reads the poll status byte of the ICU. Parameters: Master_or_Slave Specifies which interrupt controller is polled Returns: Current value of poll status byte Assumptions: None Syntax: in poll_status; poll_status = Poll_Command(); Real/Protected Mode: No changes required.
Page 242: Timer/Counter Unit
TIMER/COUNTER UNIT...
Page 244: Overview
The Timer/counter Unit (TCU) has the same basic functionality as the industry-standard 82C54 counter/timer. It contains three independent 16-bit down counters, which can be driven by a pres- caled value of the processor clock or an external clock. The counters contain two count formats (binary and BCD) and six different operating modes, two of which are periodic.
Page 245: Timer/Counter Unit Signal Connections
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Therefore, the OUTn signals can drive external devices, generate interrupt requests, initiate DMA transactions or combinations of the three. Each counter operates independently. Six different counting modes are available and two count formats: binary (16 bits) or BCD (4 decades). Each operating mode allows you to program the counter with an initial count and to change this value “on the fly.”...
Page 246: Tcu Signals And Registers
10.1.1 TCU Signals and Registers Table 10-1 and Table 10-2 lists the signals and registers associated with the TCU. Device Pin or Signal Internal Signal PSCLK Internal signal TMRCLK0 Device pin TMRCLK1 TMRCLK2 TMRGATE0 Device pin TMRGATE1 TMRGATE2 TMROUT0 Device pin TMROUT1 TMROUT2 Table 10-1.
Page 247: Tcu Associated Registers
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Table 10-2. TCU Associated Registers Expanded PC/AT* Register Address Address P3CFG 0F824H — PINCFG 0F826H (read/write) TMRCFG 0F834H — (read/write) TMRCON 0F043H 0043H TMR0 0F040H 0040H TMR1 0F041H 0041H TMR2 0F042H 0042H 10-4 Function Peripheral Pin Selections: These registers determine whether a counter’s input and output signals are connected to package pins.
Page 248: Tcu Operation
TIMER/COUNTER UNIT 10.2 TCU OPERATION Each counter can operate in any one of six operating modes. These modes are described in sec- tions 10.2.1 through 10.2.6. In all modes, the counters decrement on the falling edge of CLKINn. In modes 0, 1, 4, and 5, the counters roll over to the highest count, either 0FFFFH for binary counting or 9999 for BCD counting, and continue counting down.
Page 249: Mode 0 - Interrupt On Terminal Count
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Table 10-3. Operations Caused by GATE n Operating Low or Falling Modes Disables counting — 1) Disables counting 2) Sets OUT n immediately high 1) Disables counting 2) Sets OUT n immediately high Disables counting —...
Page 250: Mode 0 – Disabling The Count
Control Count = 4 Word = 10H Writes to Counter n CLKIN n GATE n OUT n Count Figure 10-2. Mode 0 – Basic Operation Figure 10-3 shows suspending the counting sequence. A low level on GATEn causes the counter to suspend counting (both the state of OUTn and the count remain unchanged).
Page 251: Mode 1 - Hardware Retriggerable One-Shot
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Figure 10-4 shows writing a new count before the current count reaches zero. The counter loads the new count on the CLKINn pulse after you write it, then decrements this new count on each succeeding CLKINn pulse.
Page 252: Mode 1 – Retriggering The One-Shot
Control Count = 3 Word = 12H Writes to Counter n CLKIN n GATE n OUT n Count Figure 10-5. Mode 1 – Basic Operation Figure 10-6 shows retriggering the one-shot. On the CLKINn pulse following the retrigger, the counter reloads the count. The control logic then decrements the count on each succeeding CLKINn pulse;...
Page 253: Mode 2 - Rate Generator
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Figure 10-7 shows writing a new count. The counter waits for a gate-trigger to load the new count. The counter loads the new count on the CLKINn pulse following the trigger, then decrements the count on each succeeding CLKINn pulse.
Page 254: Mode 2 – Disabling The Count
Control Count = 3 Word= 14H Writes to Counter n CLKIN n GATE n OUT n Count Figure 10-8. Mode 2 – Basic Operation Figure 10-9 shows suspending the counting sequence. A low level on GATEn causes the counter to suspend counting. The count remains unchanged and OUTn is immediately driven (or stays) high (If the GATEn goes low when OUTn is low, then OUTn is immediately driven high).
Page 255: Mode 3 - Square Wave
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Figure 10-10 shows writing a new count. The counter loads the new count after the counter reach- es one. When the counter receives a gate-trigger after a new count was written to it, the counter loads the new count on the next CLKINn pulse.
Page 256: Mode 3 – Basic Operation (Even Count)
Control Count = 4 Word = 16H Writes to Counter CLKIN GATE Count Figure 10-11. Mode 3 – Basic Operation (Even Count) Odd count basic operation: After a control word write, OUTn is driven high. On the CLKINn pulse following a gate-trigger or when the count rolls over, count minus one is loaded.
Page 257: Mode 3 – Basic Operation (Odd Count)
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Control Count = 5 Word = 16H Writes to Counter n CLKIN n GATE n OUT n Count Figure 10-12. Mode 3 – Basic Operation (Odd Count) For an even count of N, OUTn remains high for N/2 counts and low for N/2 counts (provided GATEn remains high).
Page 258: Mode 3 – Writing A New Count (Without A Trigger)
Figure 10-14 and Figure 10-15 shows writing a new count. If the counter receives a gate-trigger after writing a new count but before the end of the current half-cycle, the count is loaded on the next CLKINn pulse and counting continues from the new count (Figure 10-14). Otherwise, the new count is loaded at the end of the current half-cycle (Figure 10-15).
Page 259: Mode 4 - Software-Triggered Strobe
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.2.5 Mode 4 – Software-triggered Strobe Initializing a counter for mode 4 drives the counter’s OUTn signal high and initiates counting. A count is loaded on the CLKINn pulse following a count write. When the counter reaches zero, OUTn strobes low for one clock pulse.
Page 260: Mode 4 – Disabling The Count
Figure 10-17 shows suspending the counting sequence. A low level on GATEn causes the counter to suspend counting (both the state of OUTn and the count remain unchanged). A high level on GATEn resumes counting. Control Count = 3 Word = 18H Writes to Counter n CLKIN n...
Page 261: Mode 5 - Hardware-Triggered Strobe
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.2.6 Mode 5 – Hardware-triggered Strobe Initializing a counter for mode 5 sets the counter’s OUTn signal, starting the counting sequence. A gate-trigger loads the programmed count. When the counter reaches zero, OUTn strobes low for one clock pulse.
Page 262: Mode 5 – Retriggering The Strobe
Figure 10-20 shows retriggering the strobe with a gate-trigger. On the CLKINn pulse following the retrigger, the counter reloads the count. The control logic then decrements the count on each succeeding CLKINn pulse. OUTn remains high until the count reaches zero, then strobes low for one CLKINn pulse.
Page 263: Register Definitions
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3 REGISTER DEFINITIONS The following sections describe how to configure a counter’s input and output signals, initialize a counter for a specific operating mode and count format, write count values to a counter, and read a counter’s status and count.
Page 264: Timer Configuration Register (Tmrcfg)
Timer Configuration TMRCFG (read/write) TMRDIS SWGTEN GT2CON Number Mnemonic TMRDIS Timer Disable: 0 = Enables the CLKIN n signals. 1 = Disables the CLKIN n signals. SWGTEN Software GATE n Enable 0 = Connects GATE n to either the V 1 = Enables GT2CON, GT1CON, and GT0CON to control the GT2CON Gate 2 Connection:...
Page 265: Port 3 Configuration Register (P3Cfg)
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL The peripheral pin selection registers (P3CFG and PINCFG) determine whether each counter’s OUTn signal is connected to its TMROUTn pin. See Figure 10-1 for the TCU signal connections. For details on the P3CFG and PINCFG registers see Figure 10-23 and Figure 10-24. The counter output signals are automatically connected to the interrupt control unit.
Page 266: Pin Configuration Register (Pincfg)
Use PINCFG bit 5 to connect TMROUT2, TMRCLK2, and TMRGATE2 to package pins. Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
Page 267: Initializing The Counters
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3.2 Initializing the Counters The timer control register (TMRCON) has three formats: control word, counter-latch, and read- back. When writing to TMRCON, certain bit settings determine which format is accessed. Use the TMRCON’s control word format (Figure 10-25) to specify a counter’s count format and operating mode.
Page 268: Timer Control Register (Tmrcon – Control Word Format)
Timer Control (Control Word Format) TMRCON Number Mnemonic 7–6 SC1:0 Select Counter: Use these bits to specify a particular counter. The selections you make for bits 5–0 define this counter’s operation. 00 = counter 0 01 = counter 1 10 = counter 2 11 is not an option for TMRCON’s control word format.
Page 269: Writing The Counters
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3.3 Writing the Counters Use the write format of a counter’s Timer n register (TMRn) to specify a counter’s count. The count must conform to the write selection specified in the control word (least-significant byte only, most-significant byte only, or least-significant byte followed by the most-significant byte).
Page 270: Reading The Counter
10.3.4 Reading the Counter To read the counter you can perform a simple read operation or send a latch command to the counter. TMRCON contains two formats that allow you to send latch commands to individual counters: the counter-latch and read-back format. The counter-latch command latches the count of a specific counter.
Page 271: Timer Control Register (Tmrcon – Counter-Latch Format)
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Timer Control (Counter-latch Format) TMRCON Number Mnemonic 7–6 SC1:0 Select Counter: These bits specify the counter that receives the counter-latch command. 00 = counter 0 01 = counter 1 10 = counter 2 11 is not an option for TMRCON’s counter-latch format. Selecting 11 accesses TMRCON’s read-back format, which is shown in Figure 10-29.
Page 272: Timer N Register (Tmr N – Read Format)
You can interleave reads and writes of the same counter; for example, if the counter is pro- grammed for the two-byte read/write selection, the following sequence is valid. Read least-significant byte. Write new least-significant byte. Read most-significant byte. Write new most-significant byte. Timer n (Read Format) TMR n ( n = 0–2) Number...
Page 273: Read-Back Command
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL 10.3.4.3 Read-back Command Use the read-back format of TMRCON (Figure 10-29) to latch the count and/or status of one or more counters. Latch a counter’s status to check its programmed operating mode, count format, and read/write selection and to determine whether the latest count written to it has been loaded.
Page 274 TIMER/COUNTER UNIT The read-back command can latch the count and status of multiple counters. This single com- mand is functionally equivalent to several counter-latch commands, one for each counter latched. Each counter's latched count and status is held until it is read or until you reconfigure the counter. A counter’s latched count or status is automatically unlatched when read, but other counters’...
Page 275: Timer N Register (Tmr N – Status Format)
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Timer n (Status Format) TMR n ( n = 0–2) OUTPUT NULCNT Number Mnemonic OUTPUT Output Status: This bit indicates the current state of the counter’s output signal. 0 = OUT n is low 1 = OUT n is high NULCNT Count Status:...
Page 276: Programming Considerations
When a counter receives multiple read-back commands, it ignores all but the first command; the count/status that the core reads is the count/status latched from the first read-back command (see Table 10-6). Table 10-6. Results of Multiple Read-back Commands Without Reads Command Read-back Command Sequence...
Page 277: Timer/Counter Unit Code Examples
Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL • With the readback command: — If both the status and counter values are latched, the user can read the value of the Read/Write selection bits from the status register to know what bytes of the counter value are being latched in the TMRn register.
Page 278 Returns:Error Codes E_INVALID_DEVICE E_OK Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set); This function also initializes the Timer-Counter Unit to be in the Read/Write Format of least-significant byte first, then most-significant byte Syntax: int error; error = InitTimer Real/Protected Mode: No changes required.
Page 279 Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL if(!Enable) TmpByte |= 0x80; TmpByte |= (Inputs << (Unit*2)); _SetEXRegByte(TMRCFG,TmpByte); /* Set Timer Control Register */ TmpByte = Unit << 6; TmpByte |= (0x30 | Mode); _SetEXRegByte(TMRCON,TmpByte); /* Set Initial Counter Value */ TmpByte = HIBYTE(InitCount); _SetEXRegByte(TmrCntPort, LOBYTE(InitCount));...
Page 280 #define DISABLE SetUp_ReadBack(DISABLE, DISABLE, ENABLE, ENABLE, ENABLE); Real/Protected Mode: No changes required *****************************************************************************/ void SetUp_ReadBack( BYTE Timer0, BYTE Timer1, BYTE Timer2, BYTE GetStatus, BYTE GetCount ) BYTE rb_control = 0; rb_control |= 0xc0; // Set TMRCON to read-back command if (GetStatus != 0) rb_control &= 0xef;...
Page 281 Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL Returns: Counter Value of specified timer Assumptions: This function assumes that the R/W format is configured to be LSB first, then MSB Syntax: WORD Counter_Value; Counter_Value = CounterLatch(TMR_1); Real/Protected Mode: No changes required *****************************************************************************/ WORD CounterLatch( BYTE Timer ) BYTE control_word = 0;...
Page 282 /***************************************************************************** ReadCounter: Description: This function performs a simple read operation on the specified timer. However, because the counter value is not latched, the timer must be disabled, read, and then re-enabled. Parameters: Timer Unit number of Timer whose count is being read Returns: Counter value that was read Assumptions:...
Page 283 Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL case TMR_2: CountL = _GetEXRegByte(TMR2); CountH = _GetEXRegByte(TMR2); break; Count = (((WORD)CountH << 8) + CountL); EnableTimer(); return(Count); }/* ReadCounter */ /***************************************************************************** TimerISR: Description: Interrupt Service Routine for Timer-generated interrupts. Parameters: None Returns: None Assumptions: None Syntax:...
Page 284 /***************************************************************************** Example of how to write a new initial counter value to a timer This value can be rewritten at any time without affecting the Counter’s programmed mode. Before writing an initial count value, the Control Word must be configured for the proper R/W and Count formats. -->This example assumes that Timer1 is in the R/W format of LSB first, then MSB, and that the Count format is binary.
Page 286: Asynchronous Serial I/O Unit
ASYNCHRONOUS SERIAL I/O UNIT...
Page 288: Overview
ASYNCHRONOUS SERIAL I/O UNIT The asynchronous serial I/O (SIO) unit provides a means for the system to communicate with ex- ternal peripheral devices and modems. The SIO unit performs serial-to-parallel conversions on data characters received from a peripheral device or modem and parallel-to-serial conversions on data characters received from the CPU.
Page 289: Serial I/O Unit 1 Configuration
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SIOCFG.1 SIO1 BCLKIN Receive Data SIOINT1 RBFDMA1 TXEDMA1 Transmit Data SIOCFG.7 Clear to Send Request to Send Data Set Ready Data Carrier Detect Data Terminal Ready Ring Indicator † Alternate pin signals are in parentheses. Figure 11-1.
Page 290: Sio Signals
11.1.1 SIO Signals Table 11-1 lists the SIOn signals. Device Pin or Signal Internal Signal Baud-rate Internal signal Generator Device pin Clock Source (input) TXD n Device pin (output) RXD n Device pin (input) CTS n # Device pin (input) DSR n # Device pin (input)
Page 291: Sio Operation
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Device Pin or Signal Internal Signal TXEDMA n Internal Signal RBFDMA n Internal Signal 11.2 SIO OPERATION The following sections describe the operation of the baud-rate generator, transmitter, and receiver and discusses the modem control logic, SIO diagnostic mode, and SIO interrupt sources. 11.2.1 Baud-rate Generator Each SIO channel’s baud-rate generator provides the clocking source for the channel’s transmitter and receiver.
Page 292: Maximum And Minimum Output Bit Rates
The baud-rate generator’s output frequency is determined by BCLKIN and a divisor as follows. baud-rate generator output frequency baud rate generator output frequency bit rate -------------------------------------------------------------------------------------------------- - The minimum divisor value is 1, giving a maximum baud rate of BCLKIN. The maximum divisor value is 0FFFFH (65535), giving a minimum of BCLKIN/65535.
Page 293: Sio N Transmitter
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.2.2 SIO n Transmitter The data frame for transmissions is programmable. It consists of a start bit, 5 to 8 data characters, an optional parity bit, and 1 to 2 stop bits. The transmitter can produce even, odd, forced, or no parity.
Page 294: Sio N Transmitter
SIO n Transmit Shift Register SIO n Transmit Buffer The transmitter contains a transmitter empty (TE) flag and a transmit buffer empty (TBE) flag. At reset, TBE and TE are set, indicating that the transmit buffer and shift register are empty. Writ- ing data to the transmit buffer clears TBE and TE.
Page 295: Sio N Data Transmission Process Flow
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Select the data frame. (Word length, number of stop bits, and type of parity.) Enable interrupts and/or DMA. More Data to Transmit Figure 11-4. SIO n Data Transmission Process Flow 11-8 Select the BCLKIN source and the transmitter input baud rate.
Page 296: Sio N Receiver
11.2.3 SIO n Receiver The data frame for receptions is programmable, and is identical to the data frame for transmis- sions. It consists of a start bit, 5 to 8 data characters, an optional parity bit, and 1 to 2 stop bits. The receiver can be programmed for even, odd, forced, or no parity.
Page 297 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The receiver contains a receive buffer full (RBF) flag and flags for each of the error conditions described above. At reset, RBF and each of the error flags (PE, FE, OE, and BI) are clear, indi- cating that the receive buffer is empty, and no error has occurred.
Page 298: Sio N Data Reception Process Flow
Select the BCLKIN source and the receiver input baud rate. Select the data frame. (Word length, number of stop bits, and type of parity.) Enable interrupts and/or DMA. Receiver shifts data into shift register from the RXD n pin. a parity error detected? Receiver sets the parity error flag.
Page 299: Modem Control
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.2.4 Modem Control The modem control logic provides interfacing for four input signals and two output signals used for handshaking and status indication between the SIOn and a modem or data set. An external modem or data set uses the input signals to inform the SIOn when: •...
Page 300: Sio Interrupt And Dma Sources
11.2.6 SIO Interrupt and DMA Sources 11.2.6.1 SIO Interrupt Sources Each SIO channel has four status signals: receiver line status, receiver buffer full, transmit buffer empty, and modem status. An overrun error, parity error, framing error, or break condition can activate the receiver line status signal.
Page 301: External Uart Support
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.2.7 External UART Support Many PC compatible applications may need to support COM3 and COM4 serial ports. Since the integrated serial ports are mapped to I/O addresses that support only COM1 and COM2, an inter- face to support an external serial I/O unit has been included.
Page 302: Register Definitions
11.3 REGISTER DEFINITIONS Table 11-5 lists the registers associated with the SIO unit and the following sections contain bit descriptions for each register. Table 11-5. SIO Registers (Sheet 1 of 2) Expanded PC/AT* Register Address Address PINCFG 0F826H — (read/write) P1CFG 0F820H —...
Page 303: Access To Multiplexed Registers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 11-5. SIO Registers (Sheet 2 of 2) Expanded PC/AT* Register Address Address IIR0 0F4FAH 03FAH IIR1 0F8FAH 02FAH (read only) MCR0 0F4FCH 03FCH MCR1 0F8FCH 02FCH (read/write) MSR0 0F4FEH 03FEH MSR1 0F8FEH 02FEH (read/write) SCR0 0F4FFH...
Page 304: Pin Configuration Register (Pincfg)
11.3.1 Pin and Port Configuration Registers (PINCFG and P n CFG [ n = 1–3]) Use PINCFG bits 2:0 to connect the SIO1 signals to package pins. Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit.
Page 305: Port 1 Configuration Register (P1Cfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Use P1CFG bits 4:0 to connect SIO0 signals to package pins. Port 1 Configuration P1CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P1.7 at the package pin. 1 = Selects HLDA at the package pin. Pin Mode: 0 = Selects P1.6 at the package pin.
Page 306: Port 2 Configuration Register (P2Cfg)
Use P2CFG bits 7–5 to connect SIO0 signals to package pins. Port 2 Configuration P2CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. Pin Mode: 0 = Selects P2.6 at the package pin. 1 = Selects TXD0 at the package pin.
Page 307: Port 3 Configuration Register (P3Cfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Use P3CFG bit 7 to connect the COMCLK pin to the package pin. Port 3 Configuration P3CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P3.7 at the package pin. 1 = Selects COMCLK at the package pin. Pin Mode: 0 = Selects P3.6 at the package pin.
Page 308: Sio And Ssio Configuration Register (Siocfg)
11.3.2 SIO and SSIO Configuration Register (SIOCFG) Use SIOCFG to select the baud-rate generator clock source for the SIO channels and to have a channel’s modem input signals connected internally rather than to package pins. Selecting the in- ternal modem signal connection option connects RTS# to CTS#, DTR# to DSR# and DCD#, and to RI#.
Page 309: Divisor Latch Registers (Dll N And Dlh N )
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.3 Divisor Latch Registers (DLL n and DLH n ) Use these registers to program the baud-rate generator’s output frequency. The baud-rate gener- ator’s output determines the transmitter and receiver bit times. Divisor Latch Low DLL0, DLL1 (read/write) Divisor Latch High...
Page 310: Transmit Buffer Register (Tbr N )
11.3.4 Transmit Buffer Register (TBR n ) Write the data words to be transmitted to TBRn. Use the interrupt control or DMA units or poll the serial line status register (LSRn) to determine whether the transmit buffer is empty. Transmit Buffer TBR0, TBR1 (write only) Number...
Page 311: Receive Buffer Register (Rbr N )
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.5 Receive Buffer Register (RBR n ) Read RBRn to obtain the last data word received. Use the interrupt control or DMA units or poll the serial line status register (LSRn) to determine whether the receive buffer is full. Receive Buffer RBR0, RBR1 (read only)
Page 312: Serial Line Control Register (Lcr N )
11.3.6 Serial Line Control Register (LCR n ) Use LCRn to provide access to the multiplexed registers, send a break condition, and determine the data frame for receptions and transmissions. Serial Line Control LCR0, LCR1 (read/write) DLAB Number Mnemonic DLAB Divisor Latch Access Bit: This bit determines which of the multiplexed registers is accessed.
Page 313: Serial Line Status Register (Lsr N )
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.7 Serial Line Status Register (LSR n ) Use LSRn to check the status of the transmitter and receiver. Serial Line Status LSR0, LSR1 (read only) — Number Mnemonic — Reserved. This bit is undefined. Transmitter Empty: The transmitter sets this bit to indicate that the transmit shift register and transmit buffer register are both empty.
Page 314: Interrupt Enable Register (Ier N )
11.3.8 Interrupt Enable Register (IER n ) Use IERn to connect the SIOn status signals to the interrupt control unit. All four status signals can be connected to the interrupt control unit. Interrupt Enable IER0, IER1 (read/write) — — — Number Mnemonic 7–4...
Page 315: Interrupt Id Register (Iir N )
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.9 Interrupt ID Register (IIR n ) Use the IIRn to determine whether an interrupt is pending and, if so, which status signal generated the interrupt request. Interrupt ID IIR0, IIR1 (read only) — —...
Page 316: Modem Control Register (Mcr N )
11.3.10 Modem Control Register (MCR n ) Use MCRn to put the SIOn into a diagnostic test mode. In this mode, the modem input signals are disconnected from the package pins and controlled by the lower four MCRn bits and the mo- dem output signals are forced to their inactive states (Figure 11-19).
Page 317: Modem Control Register (Mcr N )
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Modem Control MCR0, MCR1 (read/write) — — — Number Mnemonic 7–5 — Reserved; for compatibility with future devices, write zeros to these bits. LOOP Loop Back Test Mode: 0 = Normal mode 1 = Setting this bit puts the SIO n into diagnostic (or loop back test) mode. This causes the SIO channel to: •...
Page 318: Modem Status Register (Msr N )
11.3.11 Modem Status Register (MSR n ) Read MSRn to determine the status of the modem control input signals. The upper four bits reflect the current state of the modem input signals and the lower four bits indicate whether the inputs (except for RI#) have changed state since the last time this register was read.
Page 319: Scratch Pad Register (Scr N )
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 11.3.12 Scratch Pad Register (SCR n ) SCRn is available for use as a scratch pad. Writing and reading this register has no effect on SIOn operation. Scratch Pad SCR0, SCR1 (read/write) Number Mnemonic Writing and reading this register has no effect on SIO n operation.
Page 320: Asynchronous Serial I/O Unit Code Examples
11.4.1 Asynchronous Serial I/O Unit Code Examples The code example contains these software routines: InitSIO Initializes the SIO for asynchronous transfers SerialReadStr Polled serial read function that reads a specified number of characters SerialReadChar Polled serial read function that reads a single character SerialWriteChar Polled serial write function that writes a single character SerialWriteStr...
Page 321 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL options ModemCntrl Defines the operation of the modem control lines BaudRate Specifies baud rate. The baud divisor value is calculated based on clocking source and clock frequency. The clocking frequency is set by calling the InitializeLibrary function.
Page 322 return E_INVALID_DEVICE; /* Set Port base based on serial port used */ SIOPortBase = (Unit ? SIO1_BASE : SIO0_BASE); /* Initialized Serial Port registers */ /* Calculate the baud divisor value, based on baud clocking */ BaudDivisor = (WORD)(BaudClkIn / (16*BaudRate)); /* Turn on access to baud divisor register */ _SetEXRegByte(SIOPortBase + LCR, 0x80);...
Page 323 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define SIO_0 #define LENGTH 32 char String_Read[LENGTH]; int error; error = SerialReadStr (SIO_0, String_Read, LENGTH); Real/Protected Mode No changes required. *****************************************************************************/ int SerialReadStr(int Unit, char far *str, int count) WORD ReceivePortAddr; WORD StatusPortAddr; BYTE Status; int i;...
Page 324 until a character has been received from the serial port. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. Returns: BYTE Read from serial port, if zero an error occurred. Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
Page 325 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SerialWriteChar: Description: Is a Polled serial port write function that waits forever or until a character has been written to the serial port. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1.
Page 326 Description: Is a Polled serial port write function that waits forever or until all characters have been written to the serial port. The NUL character (‘\0’) is used to indicate end of string. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1.
Page 327 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /***************************************************************************** SerialWriteMem: Description: Is a Polled serial port write function that waits forever or until count characters have been written to the serial port. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1.
Page 328 } /* SerialWriteMem */ /***************************************************************************** Serial0_ISR: Description: Template Interrupt Service Routine for Serial Port0 interrupts. This function identifies the cause of the interrupt and branches to the corresponding action. Parameters: None (Not called by user) Returns: None Assumptions: None Syntax: Not a user function.
Page 329 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL if ((msr0 & 0x04) && (msr0 & 0x40)) { /* ring indicator */ if ((msr0 & 0x02) && (msr0 & 0x20)) { /* data set ready bit has been set */ if ((msr0 & 0x01) && (msr0&0x10)) { /* clear to send signal has been set */ break;...
Page 330 /***************************************************************************** Service_RBF: Description: Service routine for interrupts generated by RBF signal. This routine is used for Interrupt-Driven Serial Reads. It echoes the typed character to the screen, stopping when it receives an ESC character. Parameters: None Returns: None Assumptions: None Syntax: Not called by user Real/Protected Mode:...
Page 331 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Description: Is an interrupt driven serial port write function. The NUL character (‘\0’) is used to indicate end of string. Parameters: Unit Unit number of the serial port. 0 for SIO port 0, 1 for SIO port 1. Address of a zero terminated string to be transmitted Returns: None...
Page 332 None Assumptions: None Syntax: Not called by user. Real/Protected Mode: No changes required. ******************************************************************************/ void Service_TBE(void) if (trans_buffer[Tbuffer_index] != ‘\0’) { _SetEXRegByte(TBR0, trans_buffer[Tbuffer_index]); Tbuffer_index++; else { /* Disable TBE interrupts */ _SetEXRegByte(IER0, 0x00); }/* Service_TBE */ /**************************************************************************** Example code to show how to set up for a Serial Port interrupt. This example is for an interrupt on SIO_0 sourced by the Receive Buffer Full Signal.
Page 334: Dma Controller
CONTROLLER...
Page 336: Overview
The DMA controller improves system performance by allowing external or internal peripherals to directly transfer information to or from the system. The DMA controller can transfer data be- tween any combination of memory and I/O, with any combination of data path widths (8 or 16 bits).
Page 337: Dma Unit Block Diagram
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DMACFG.2:0 DREQ0 DMACFG.3 DMAACK0# DMACFG.6:4 DREQ1 DMACFG.7 DMAACK1# DMAINT To ICU End of Process HOLD Bus Arbiter HLDA † Alternate pin signals are in parentheses. Figure 12-1. DMA Unit Block Diagram 12-2 RBFDMA0 (SIO0) To SIO1 TXEDMA1 (SIO1) SSTBE (SSIO)
Page 338: Dma Terminology
12.1.1 DMA Terminology This section provides a definition of some of the terms used in this chapter to describe the DMA controller. DMA Process A DMA process is the execution of a programmed DMA task from beginning to end. Each DMA process requires initial programming by the Intel386 EX processor.
Page 339: Dma Signals
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.1.2 DMA Signals Table 12-1 describes the DMA signals. Signal DRQ0 SIO0 RBFDMA0/TXEDMA0 SIO1 TXEDMA1/RBFDMA1 SSIO Transmitter/Receiver TCU Counter 1 DRQ1 SIO1 RBFDMA1/TXEDMA1 SIO0 TXEDMA0/RBFDMA0 SSIO Receiver/Transmitter TCU Counter 2 DACK n # EOP# 12-4 Table 12-1.
Page 340: Dma Operation
12.2 DMA OPERATION The following sections describe the operation of the DMA. See “Register Definitions” on page 12-28 for details on implementing DMA Controller options. 12.2.1 DMA Transfers The DMA transfers data between a requester and a target. The data can be transferred from the requester to target or vice versa.
Page 341: Two-Cycle Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL data bus, depending on the transfer direction. Since the requester is selected via the DACKn# sig- nal the requester address is not meaningful in a fly-by mode transfer. Support logic (either external or built in to the I/O device) must be designed to monitor the DACKn# signal and accordingly generate the correct control signals to the I/O device, since all processor signals are used to access memory.
Page 342: Ready Generation For Dma Cycles
DMACFG register), but the Requester address registers would be programmed with one of the memory addresses. It doesn’t really matter which memory is the Requester and which is the Tar- get, as long as the transfer direction is set to provide the correct Source and Destination. 12.2.2.4 Ready Generation For DMA Cycles DMA cycles are identical to any other type of memory or I/O cycles in terms of how they are...
Page 343: Dma Temporary Buffer Operation For A Write Transfer
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Figures 12-2 and 12-3 are simple diagrams of how the Temporary Register is filled and emptied for a Read DMA cycle and a Write DMA cycle. Filling the Temporary Register DREQ n DREQ n DREQ n Four separate requests each with a read of the requester.
Page 344: Starting Dma Transfers
12.2.3 Starting DMA Transfers Internal I/O, external I/O, or memory can request DMA service. The internal I/O requesters (the asynchronous serial I/O, synchronous serial I/O, and timer control units) are internally connected to the DMA request inputs. You must connect an external I/O source to the DMA DRQn; when you are using fly-by mode, you must also connect an external I/O source to the DACKn# signals.
Page 345: Ending Dma Transfers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL control request, the bus arbiter services these requests by issuing an internal hold signal request- ing control of the bus from the core. The core returns an internal hold acknowledge signal to the arbiter when bus ownership is granted. The arbiter then issues an acknowledge signal to the re- questing device.
Page 346: Buffer Transfer Ended By An Expired Byte Count
DMA CONTROLLER Terminating a buffer transfer by deasserting DREQn can also be done either synchronously or asynchronously. The effect is identical to that of synchronous or asynchronous sampling of EOP#. When DREQn is used to terminate a DMA transfer in asynchronous mode, DREQn must be sampled inactive one CLKOUT before READY#.
Page 347: Buffer-Transfer Modes
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.2.6 Buffer-transfer Modes After a buffer transfer is completed or terminated, a channel can either become idle (require re- programming) or reprogram itself and begin another buffer transfer after it is initiated by a hard- ware or software request.
Page 348: Data-Transfer Modes
The DMAINT signal is active immediately after the Chaining Process has been entered, as the channel then perceives the Base Registers to be empty and in need of reloading. It is important to have the interrupt service routine in place at the time the Chaining Process is entered. The inter- rupt request is removed when the most significant byte of the Base Target Address is loaded.
Page 349: Single Data-Transfer Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL transfer is suspended and the channel waits for the request input to be reactivated before it continues. 12.2.7.1 Single Data-transfer Mode In single data-transfer mode, a DMA request causes the channel to gain bus control. The channel transfers data (a byte or a word), decrements the buffer byte count (by 1 for byte transfers and 2 for word transfers), then relinquishes bus control.
Page 350: Single Data-Transfer Mode With Single Buffer-Transfer Mode
DMA CONTROLLER After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQ n active? DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. DMA channel relinquishes bus control. Byte count = FFFFFFH or EOP#...
Page 351: Single Data-Transfer Mode With Autoinitialize Buffer-Transfer Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initialization, the DMA channel is DMA transfers one byte or word of data DMA channel relinquishes bus control. DMA channel is reprogrammed with the Figure 12-9. Single Data-transfer Mode with Autoinitialize Buffer-transfer Mode 12-16 programmed with the requester and target addresses and a byte count.
Page 352: Single Data-Transfer Mode With Chaining Buffer-Transfer Mode
After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DMA gains bus control, transfers one byte or word of data, decrements byte count, and then relinquishes bus control. DMA is programmed with the new addresses and byte count.
Page 353: Block Data-Transfer Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.2.7.2 Block Data-transfer Mode In block data-transfer mode, a channel request initiates a buffer transfer. The channel gains bus control, then transfers the entire buffer of data. The DRQn signal only needs to be held active until DACKn# is active.
Page 354: Block Data-Transfer Mode With Single Buffer-Transfer Mode
DMA CONTROLLER After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQ n active? DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count. Byte count = FFFFFFH or EOP# active?
Page 355: Block Data-Transfer Mode With Autoinitialize Buffer-Transfer Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL After initiallization, the DMA channel is programmed with the requester and target DMA transfers one byte or word of data DMA channel relinquishes bus control. DMA channel is reprogrammed with the Figure 12-12. Block Data-transfer Mode with Autoinitialize Buffer-transfer Mode 12-20 addresses and a byte count.
Page 356: Demand Data-Transfer Mode
DMA CONTROLLER 12.2.7.3 Demand Data-transfer Mode In demand data-transfer mode, a channel request initiates a buffer transfer. The channel gains bus control and begins the buffer transfer. As long as the request signal (DRQn) remains active, the channel continues to perform data transfers. When the DRQn signal goes inactive, the channel completes its current bus cycle and relinquishes bus control, suspending the buffer transfer.
Page 357: Demand Data-Transfer Mode With Single Buffer-Transfer Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DMA channel relinquishes bus control. Figure 12-14. Demand Data-transfer Mode with Single Buffer-transfer Mode 12-22 After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQ n active? DMA gains bus control.
Page 358: Demand Data-Transfer Mode With Autoinitialize Buffer-Transfer Mode
DMA channel DREQ n relinquishes active? bus control. Figure 12-15. Demand Data-transfer Mode with Autoinitialize Buffer-transfer Mode After initialization, the DMA channel is programmed with the requester and target addresses and a byte count. DREQ n active? DMA gains bus control. DMA transfers one byte or word of data and decrements the byte count.
Page 359: Demand Data-Transfer Mode With Chaining Buffer-Transfer Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Write new requester Is there and target a new process addresses to set up? and a new byte count. DMA channel relinquishes bus control. Figure 12-16. Demand Data-transfer Mode with Chaining Buffer-transfer Mode 12-24 After initialization, the DAM channel is programmed with the requester and target addresses and a byte count.
Page 360: Cascade Mode
12.2.8 Cascade Mode Cascade mode allows an external 8237A or another DMA-type device to gain bus control. A cas- caded device requests bus control by holding a channel’s request input (DRQn) active. Once granted bus control, the cascaded device remains bus master until it relinquishes bus control by deactivating DRQn.
Page 361: Cascade Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Cascaded Refresh device cycle is deasserts performed. DRQ n , relinquishing bus control. 12.2.9 DMA Interrupts Each channel contains two interrupt causing signals, chaining status and transfer complete. When a channel is configured for the chaining buffer-transfer mode, the chaining status signal indicates that the channel has started its buffer transfer and new transfer information can be written without affecting the current buffer transfer.
Page 362: 8237A Compatibility
The four interrupt source signals (two per channel) are internally connected (ORed) to the inter- rupt request output (DMAINT). When an interrupt from DMAINT is detected, you can determine which signal caused the request by reading the DMA interrupt status register. 12.2.10 8237A Compatibility Although the DMA is an enhancement over the 8237A, you can configure it to operate in an 8237A-compatible mode.
Page 363: Register Definitions
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3 REGISTER DEFINITIONS Table 12-3 lists the registers associated with the DMA unit, and the following sections contain bit descriptions for each register. Table 12-3. DMA Registers (Sheet 1 of 3) Expanded Register Address PINCFG F826H —...
Page 364 Table 12-3. DMA Registers (Sheet 2 of 3) Expanded Register Address DMASTS F008H 0008H (read only) DMACMD2 F01AH — (write only) DMAMOD1 F00BH 000BH (write only) DMAMOD2 F01BH — (write only) DMASRR F009H 0009H (read/write) DMAMSK F00AH 000AH (write only) DMAGRPMSK F00FH 000FH...
Page 365 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table 12-3. DMA Registers (Sheet 3 of 3) Expanded Register Address DMACHR F019H — (write only) DMAIEN F01CH — (read/write) DMAIS F019H — (read only) DMAOVFE F01DH — (read/write) 12-30 PC/AT* Address DMA Chaining: Enables chaining buffer-transfer mode for a specified channel.
Page 366: Pin Configuration Register (Pincfg)
12.3.1 Pin Configuration Register (PINCFG) Use PINCFG to connect DACK0#, EOP#, and DACK1# to package pins. Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin.
Page 367: Dma Configuration Register (Dmacfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.2 DMA Configuration Register (DMACFG) Use DMACFG to select one of the hardware sources for each channel and to mask the DMA ac- knowledge (DMAACKn#) signals when using internal requesters. DMA Configuration DMACFG (read/write) D1MSK D1REQ2 D1REQ1...
Page 368: Channel Registers
12.3.3 Channel Registers To program a DMA channel’s requester and target addresses and its byte count, write to the DMA channel registers. Some of the channel registers require the use of a byte pointer (BP) flip-flop to control the access to the upper and lower bytes. After you write or read a register that requires a byte pointer specification, the DMA toggles the byte pointer.
Page 369: Dma Overflow Enable Register (Dmaovfe)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The value you write to the byte count register must be one less than the number of bytes to be transferred. To transfer one byte, write zero to the byte count register (byte count = number of bytes one (byte) to the byte count register (byte count = [number of words X 2] 12.3.4 Overflow Enable Register (DMAOVFE) Use DMAOVFE to specify whether all 26 bits or only the lower 16 bits of the target and requester...
Page 370: Dma Command 1 Register (Dmacmd1)
12.3.5 Command 1 Register (DMACMD1) Use DMACMD1 to enable both channels and to select the rotating method for changing the bus control priority structure. DMA Command 1 DMACMD1 (write only) — — — Number Mnemonic 7–5 — Reserved; for compatibility with future devices, write zeros to these bits. Priority Rotation Enable: 0 = Priority is fixed based on value in DMACMD2.
Page 371: Dma Status Register (Dmasts)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.6 Status Register (DMASTS) Use DMASTS to check the status of the channels individually. The DMA sets bits in this register to indicate that a channel has a hardware request pending or that a channel’s byte count has ex- pired.
Page 372: Dma Command 2 Register (Dmacmd2)
12.3.7 Command 2 Register (DMACMD2) Use DMACMD2 to select the DREQn and EOP# sampling: asynchronous or synchronous. Bus timing diagrams that show the differences between asynchronous and synchronous sampling are shown in Figure 12-5 on page 12-10 and Figure 12-13 on page 12-21. Also, use DMACMD2 to assign a particular bus request to the lowest priority level for fixed priority mode.
Page 373: Mode 1 Register (Dmamod1)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.8 Mode 1 Register (DMAMOD1) Use DMAMOD1 to select a particular channel’s data-transfer mode and transfer direction and to enable the channel’s auto-initialize buffer-transfer mode. You can configure the DMA to modify the target address during a buffer transfer by clearing DMAMOD2.2, then use DMAMOD1.5 to specify how the channel modifies the address.
Page 374: Dma Mode 1 Register (Dmamod1)
DMA Mode 1 DMAMOD1 (write only) DTM1 DTM0 Number Mnemonic 7–6 DTM1:0 Data-transfer Mode: 00 = Demand 01 = Single 10 = Block 11 = Cascade Target Increment/Decrement: 0 = Causes the target address to be incremented after each data transfer in a buffer transfer.
Page 375: Mode 2 Register (Dmamod2)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.9 Mode 2 Register (DMAMOD2) Use DMAMOD2 to select the data transfer bus cycle option, specify whether the requester and target are in memory or I/O, and determine whether the DMA modifies the target and requester addresses.
Page 376: Dma Mode 2 Register (Dmamod2)
DMA Mode 2 DMAMOD2 (write only) Number Mnemonic Bus Cycle Option: 0 = Selects the fly-by data transfer bus cycle option for the channel specified by bit 0. 1 = Selects the two-cycle data transfer bus cycle option for the channel specified by bit 0.
Page 377: Dma Software Request Register (Dmasrr – Write Format)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.10 Software Request Register (DMASRR) Write DMASRR to issue software DMA service requests. Software requests are subject to bus control priority arbitration with all other software and hardware requests. A software request ac- tivates the internal channel request signal. This signal remains active until the channel completes its buffer transfer (either by an expired byte count or an EOP# input).
Page 378: Dma Software Request Register (Dmasrr – Read Format)
Read DMASRR to see whether a software request for a particular channel is pending. Each re- quest bit is cleared upon Terminal Count or external EOP#. When in auto-initialize mode, both bits are cleared when a Terminal Count or external EOP# occurs. DMA Software Request (read format) DMASRR —...
Page 379: Channel Mask And Group Mask Registers (Dmamsk And Dmagrpmsk)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK) Use the DMAMSK and DMAGRPMSK registers to disable (mask) or enable channel hardware requests. DMAMSK allows you to disable or enable hardware requests for only one channel at a time, while DMAGRPMSK allows you to disable or enable hardware requests for both channels at once.
Page 380: Dma Group Channel Mask Register (Dmagrpmsk)
DMA Group Channel Mask DMAGRPMSK (read/write) — — — Number Mnemonic 7–2 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. HRM1 Hardware Request Mask 1: 0 = Channel 1’s hardware requests are not masked. 1 = Masks (disables) channel 1’s hardware requests.
Page 381: Dma Bus Size Register (Dmabsr)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.12 Bus Size Register (DMABSR) Use DMABSR to determine the requester and target data bus widths (8 or 16 bits). DMA Bus Size DMABSR (write only) — — Number Mnemonic — Reserved; for compatibility with future devices, write zero to this bit. Requester Bus Size: Specifies the requester’s data bus width for the channel specified by bit 0 = 16-bit bus...
Page 382: Dma Chaining Register (Dmachr)
12.3.13 Chaining Register (DMACHR) Use DMACHR to enable or disable the chaining buffer-transfer mode for a selected channel. The following steps describe how to set up a channel to perform chaining buffer transfers. Set up the chaining interrupt (DMAINT) service routine. Configure the channel for the single buffer-transfer mode.
Page 383: Dma Interrupt Enable Register (Dmaien)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.14 Interrupt Enable Register (DMAIEN) Use DMAIEN to individually connect channel 0’s and 1’s transfer complete signal to the DMAINT interrupt request output. DMA Interrupt Enable DMAIEN (read/write) — — — Number Mnemonic 7–2 —...
Page 384: Dma Interrupt Status Register (Dmais)
12.3.15 Interrupt Status Register (DMAIS) DMAIS indicates which source activated the DMA interrupt request signal (channel 0 transfer complete, channel 1 transfer complete, channel 0 chaining, or channel 1 chaining). DMA Interrupt Status DMAIS (read only) — — Number Mnemonic 7–6 —...
Page 385: Dma Software Commands
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 12.3.16 Software Commands The DMA contains four software commands: clear byte pointer, clear DMA, clear mask register, and clear transfer complete signal. Each software command has an I/O address associated with it (see Table 12-4). To issue a software command, write to its I/O address; the data written doesn’t matter —writing to the location is all that is necessary.
Page 386: Dma Controller Code Examples
with BP=0 causes the DMA to set BP. The clear byte pointer software command (DMACLRBP) allows you to force BP to a known state (0) before writing to the registers. • The target and requester addresses are incremented, decremented, or left unchanged and the byte count is decremented after each data transfer within a buffer transfer.
Page 387 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL InitDMA1ForSSIXmitterToMem DMAInterrupt See Appendix C for included header files. #include “80386ex.h” #include “ev386ex.h” #include “dma.h” #include <DOS.h> #pragma warning(disable:4704) /***************************************************************************** EnableDMAHWRequests: int EnableDMAHWRequests(int nChannel) Description: Enables channel hardware requests for the given DMA channel. Parameters: nChannel --channel to enable hardware requests...
Page 388 /***************************************************************************** DisableDMAHWRequests: Description: Disables channel hardware requests for the given DMA channel. The channel, however, can still receive software requests. Parameters: nChannel --channel to mask hardware requests Returns: Error Code Assumptions: None Syntax: int error_code; error_code = DisableDMAHWRequests(DMA_Channel0); Real/Protected Mode: No changes required *****************************************************************************/ int DisableDMAHWRequests(int nChannel)
Page 389 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Description: Sets the requester to an I/O port address, wIO, for the DMA channel specified by nChannel. Parameters: nChannel --channel for which to set Requester I/O port address --I/O address Returns: None Assumptions: None Syntax: SetDMAReqIOAddr(DMA_Channel1, TBR0);...
Page 390 Description: Sets the target memory address for the DMA channel specified by nChannel. Parameters: nChannel --channel for which to set target address ptMemory --pointer to target memory location Returns: None Assumptions: Processor is in real mode. Syntax: static char lpsz[]=”Hello World”; SetDMATargMemAddr(DMA_Channel1, lpsz);...
Page 391 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #else /*Else in compact, large, or huge memory model*/ wSegment = _FP_SEG(ptMemory); wOffset = _FP_OFF(ptMemory); #endif address*/ lAddress = ((DWORD) wSegment << 4) + wOffset; _SetEXRegByte(DMACLRBP, 0x0); /* Write target address, bits 0-7 */ _SetEXRegByte(addrDMATar0_1, (BYTE) (lAddress &...
Page 392 *****************************************************************************/ int SetDMAXferCount(int nChannel, DWORD lCount) WORD addrDMAByc0_1; WORD addrDMAByc2; if ( (nChannel != DMA_Channel0) && (nChannel != DMA_Channel1) ) return ERR_BADINPUT; /*Set registers to correct channel*/ addrDMAByc0_1 = (nChannel == DMA_Channel0 ? DMA0BYC0_1 : DMA1BYC0_1); addrDMAByc2 = (nChannel == DMA_Channel0 ? DMA0BYC2 : DMA1BYC2); _SetEXRegByte(DMACLRBP, 0x0);...
Page 393 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Syntax: InitDMA(); //Initialize DMA peripheral Real/Protected Mode: No changes required *****************************************************************************/ void InitDMA(void) _SetEXRegByte(DMACLR, 0x0); _SetEXRegByte(DMACMD1, 0x0); _SetEXRegByte(DMACMD2, 0x8); /***************************************************************************** InitDMA1ForSSIXmitterToMem: Description: This function prepares DMA channel 1 for transfers between the async. serial port transmitter (channel 0) and memory. function, a DMA transfer can be initiated by setting the Target address, setting the transfer count, and clearing the hardware request mask for this DMA channel.
Page 394 SetDMATargMemAddr(DMA_Channel1, lpsz); //Set target memory address SetDMAXferCount(DMA_Channel1, strlen(lpsz) ); EnableDMAHWRequests(DMA_Channel1); Real/Protected Mode: No changes required *****************************************************************************/ void InitDMA1ForSerialXmitter(void) BYTE regDMACfg; BYTE regDMAIE; BYTE regDMAOvfE; DisableDMAHWRequests(DMA_Channel1); /*Disable channel 1 Hardware requests*/ regDMACfg = (_GetEXRegByte(DMACFG) & 0x0F) | 0xA0; _SetEXRegByte(DMACFG, regDMACfg); /*DMACFG[7]=1: mask DMA Acknowledge for*/ _SetEXRegByte(DMAMOD1, 0x9);...
Page 395 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL _SetEXRegByte(DMABSR, 0x51); /*DMABSR[7]=0: reserved*/ _SetEXRegByte(DMACHR, 0x1); /*DMACHR[7:3]=0: reserved*/ regDMAIE = _GetEXRegByte(DMAIEN) & 0x1; _SetEXRegByte(DMAIEN, regDMAIE); /*DMAIE[7:2]=untouched: reserved*/ regDMAOvfE = _GetEXRegByte(DMAOVFE) | 0xC; _SetEXRegByte(DMAOVFE, regDMAOvfE); /*DMAOVFE[7:4]=untouched: reserved*/ SetDMAReqIOAddr(DMA_Channel1, TBR0); /*Sets Req. I/O address to Serial*/ /***************************************************************************** DMAInterrupt: Description:...
Page 396 None Syntax: regDMAIE = _GetEXRegByte(DMAIEN) | 0x2; //Enable tc interrupt for _SetEXRegByte(DMAIEN, regDMAIE); //Set interrupt routine SetIRQVector(DMAInterrupt, 12, INTERRUPT_ISR); Enable8259Interrupt(0, IR4); NonSpecificEOI(); //Clear all interrupts Real/Protected Mode: No changes required *****************************************************************************/ void interrupt far DMAInterrupt(void) WORD regDMAIS; regDMAIS = _GetEXRegByte(DMAIS); /*Get interrupt status register*/ if (regDMAIS &...
Page 398: Synchronous Serial I/O Unit
SYNCHRONOUS SERIAL I/O UNIT...
Page 400: Overview
The synchronous serial I/O (SSIO) unit provides 16-bit bidirectional serial communications. The transmit and receive channels can operate independently (that is, with different clocks) to provide full-duplex communications. Either channel can originate the clocking signal or receive an exter- nally generated clocking signal. This chapter is organized as follows: •...
Page 401: Transmitter And Receiver In Master Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Clock Source (PSCLK or SERCLK) SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt controller IR1) SSIOCON.1 (RIE) SSRBF (to DMA controller) Figure 13-1. Transmitter and Receiver in Master Mode SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt...
Page 402: Baud-Rate Generator
Clock Source (PSCLK or SERCLK) STXCLK SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt controller IR1) SSIOCON.1 (RIE) SSRBF (to DMA controller) Figure 13-3. Transmitter in Slave Mode, Receiver in Master Mode STXCLK SSTBE (to DMA controller) SSIOCON.5 (TIE) SSIOINT (to Slave interrupt controller IR1)
Page 403: Ssio Signals
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.1.1 SSIO Signals Table 13-1 lists the SSIO signals. Device Pin or Signal Internal Signal STXCLK Device pin Serial Transmit Clock: (input or output) This pin functions as either an output or an input, depending on whether the transmitter is operating in master or slave mode.
Page 404: Clock Sources For The Baud-Rate Generator
13.2 SSIO OPERATION The following sections describe the operation of the baud-rate generator, transmitter, and receiv- 13.2.1 Baud-rate Generator Either the prescaled clock or the serial clock (PSCLK or SERCLK) can drive the baud-rate gen- erator (Figure 13-5). The SIO and SSIO configuration register (SIOCFG) selects one of these sources.
Page 405: Transmitter
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The baud-rate generator contains a seven-bit down counter. A programmable baud-rate value (BV) is the reload value for the counter. The counter counts down from BV to zero, toggles the baud-rate generator output, then reloads the BV and counts down again. The baud-rate genera- tor’s output is a function of BV and BCLKIN as follows.
Page 406: Transmit Mode Using Enable Bit
13.2.2.1 Transmit Mode using Enable Bit The transmitter contains a transmit holding buffer empty (THBE) flag and a transmit underrun error (TUE) flag. At reset, THBE is set, indicating that the buffer is empty. Writing data to the buffer clears THBE. When the transmitter transfers data from the buffer to the shift register, THBE is set.
Page 407: Ssio Transmitter With Autotransmit Mode Disabled
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Initialize SSIO Figure 13-7. SSIO Transmitter with Autotransmit Mode Disabled The SSIO Unit can be operated either by using a polling method or through interrupts. • Figure 13-8 shows a basic flowchart for using the polling method to transmit data through the SSIO.
Page 408: Transmit Data By Polling
Initialize SSIO Write Data to Buffer Write Data to Buffer (SSIOTBUF) (SSIOTBUF) AUTOTXM=1 Enable Transmitter TEN=1 Delay To Allow Transmitter To Shift First Bit Out Disable Transmitter Figure 13-8. Transmit Data by Polling SYNCHRONOUS SERIAL I/O UNIT THBE=1 AUTOTXM=1 TEN=0 TUE=1 Error Routine...
Page 409: Interrupt Service Routine For Transmitting Data Using Interrupts
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Delay To Allow Transmitter Exit Interrupt Service Routine Figure 13-9. Interrupt Service Routine for Transmitting Data Using Interrupts 13-10 SSIO Transmitter Causes Interrupt Disable Interrupts While Transmitting Data THBE=1 Write Data to Buffer (SSIOTBUF) Enable Transmitter TEN=1 To Shift First Bit Out...
Page 410 If the transmitter is disabled while a data value in the shift register is being shifted out, it continues running until the last bit is shifted out. Then the shift register stops and the data and clock pins (SSIOTX and STXCLK) are three-stated; the contents of the buffer register are not loaded into the shift register.
Page 411: Autotransmit Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.2.2.2 Autotransmit Mode Set the AUTOTXM bit (SSIOCON2.2) and the TXMM bit (SSIOCON2.1) to enable Autotrans- mit mode. When the AUTOTXM bit is set, the word is automatically transferred to the shift reg- ister and the THBE bit is set. In this mode the TEN bit is ignored. Once the data is transferred to the shift register, the word is shifted out.
Page 412: Receive Data By Polling
The SSIO Unit can be operated either by using a polling method or through interrupts. • Figure 13-12 shows a basic flowchart for using the polling method to receive data through the SSIO. • Figure 13-13 shows a basic flowchart for the Interrupt Service Routine necessary when using interrupts to receive data through the SSIO.
Page 413: Interrupt Service Routine For Receiving Data Using Interrupts
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SSIO Receiver Causes Interrupt Disable Interrupts While Receiving Data Read Data From Buffer (SSIORBUF) Error ROE=0 Routine Enable Interrupts Exit Interrupt Service Routine A3397-01 Figure 13-13. Interrupt Service Routine for Receiving Data Using Interrupts 13-14...
Page 414: Receiver Master Mode, Single Word Transfer
If the receiver is disabled while a data value is being shifted into the shift register, it continues running until the last bit is shifted in. Then the shift register is loaded into the buffer register, the shift register stops and the clock pin (SRXCLK) is three-stated if in the master mode. If the receiver is disabled then enabled before the current word has been shifted in, it continues as if it were never disabled.
Page 415: Register Definitions
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3 REGISTER DEFINITIONS Table 13-3 list the registers associated with the SSIO and the following sections contain bit de- scriptions for each register. Expanded Register Address PINCFG F826H Pin Configuration: (read/write) Connects the serial receive clock signal (SRXCLK) and the transmit serial data signal (SSIOTX) to the package pin.
Page 416: Pin Configuration Register (Pincfg)
13.3.1 Pin Configuration Register (PINCFG) The serial receive clock (SRXCLK) and transmit serial data (SSIOTX) pins are multiplexed with other functions. Use PINCFG bits 0 and 1 to select the pin functions. Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved.
Page 417: Sio And Ssio Configuration Register (Siocfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3.2 SIO and SSIO Configuration Register (SIOCFG) Use SIOCFG bit 2 to connect either PSCLK or SERCLK to the baud-rate generator’s input (BCLKIN). SIO and SSIO Configuration SIOCFG (read/write) — Number Mnemonic SIO1 Modem Signal Connections: 0 = Connects the SIO1 modem input signals to the package pins.
Page 418: Clock Prescale Register (Clkprs)
13.3.3 Prescale Clock Register (CLKPRS) Use CLKPRS to program the PSCLK frequency. Clock Prescale Register CLKPRS (read/write) — — — Number Mnemonic 15–9 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 8–0 PS8:0 Prescale Value: These bits determine the divisor that is used to generate PSCLK.
Page 419: Ssio Baud-Rate Control Register (Ssiobaud)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3.4 SSIO Baud-rate Control Register (SSIOBAUD) Use SSIOBAUD to enable the baud-rate generator and determine the baud-rate generator’s sev- en-bit down counter’s reload value (BV). SSIO Baud-rate Control SSIOBAUD (read/write) Number Mnemonic Baud-rate Generator Enable: Setting this bit enables the baud-rate generator.
Page 420: Ssio Baud-Rate Count Down Register (Ssioctr)
13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR) Read SSIOCTR to determine the status of the baud-rate generator. The down counter is reloaded when CV6:0 reaches zero or when a new value is written to SSIOBAUD. Baud-rate Count Down SSIOCTR (read only) BSTAT Number Mnemonic...
Page 421: Ssio Control 1 Register (Ssiocon1)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL SSIO Control 1 SSIOCON1 (read/write) THBE Number Mnemonic Transmit Underrun Error: The transmitter sets this bit to indicate a transmit underrun error in the TEN transfer mode. Clear this bit to clear the error flag. If a one is written to TUE, it is ignored and TUE retains its previous value.
Page 422: Ssio Control 2 Register (Ssiocon2)
13.3.7 SSIO Control 2 Register (SSIOCON2) Use the control bits TXMM and RXMM in SSIOCON2 to put the transmitter or receiver in mas- ter or slave mode. The AUTOTXM bit is used to determine if the TEN bit controls the transmit- ting of the data.
Page 423: Ssio Transmit Holding Buffer (Ssiotbuf)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.3.8 SSIO Transmit Holding Buffer (SSIOTBUF) Write the data words to be transmitted to SSIOTBUF. Use the interrupt controller, DMA unit or polling (read SSIOCON1) to determine when to write to the transmit buffer. Transmit Holding Buffer SSIOTBUF (read/write)
Page 424: Ssio Receive Holding Buffer (Ssiorbuf)
13.3.9 SSIO Receive Holding Buffer (SSIORBUF) Read SSIORBUF to obtain the last data word received. Use the interrupt controller, DMA unit or polling (read SSIOCON1) to determine when to read the receive buffer. Receive Holding Buffer SSIORBUF (read only) RB15 RB14 RB13 Number...
Page 425: Programming Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13.5 PROGRAMMING CONSIDERATIONS • When operating the transmitter in Master mode, and not in Autotransmit mode, you must ensure that the last character to be transmitted is in the process of being shifted out before disabling the transmitter.
Page 426 Initialization routine for Synchronous Serial I/O Port. Parameters: Mode Enables receiver and transmitter; Enables TBE and RHBF interrupts MasterTxRx Defines whether Tx and/or Rx are in Master Mode BaudValue Enables Baud-rate generator and sets Baud-rate Value PreScale 9-bit Clock prescale value Returns: None Assumptions:...
Page 427 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* Init Baud Rate Generator */ _SetEXRegByte(SSIOBAUD,BaudValue); _SetEXRegByte(SSIOCON1,Mode); _SetEXRegByte(SSIOCON2,MasterTxRx); }/* InitSSIO */ /***************************************************************************** SSerialReadWord: Description: Is a Polled serial port read function that will wait forever or until a character has been received from the serial port. Parameters: MasterSlave Defines if receiver is in Master or Slave mode...
Page 428 /* Disable Receiver */ _SetEXRegByte(SSIOCON1, SSControl); else // Slave Receiver, Receiver MUST already be Enabled /* Wait until Receive Holding Buffer is Full */ while(!(_GetEXRegByte(SSIOCON1) & SSIO_RHBF) ); return (WORD)_GetEXRegWord(SSIORBUF); }/* SSerialReadWord */ /***************************************************************************** SSerialWriteWord: Description: Is a Polled serial port write function that will wait forever or until a character has been written to the serial port.
Page 429 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /* Get Control Register Ready to disable */ SSControl &= (~SSIO_TX_ENAB); /* Set Buffer to Character */ _SetEXRegWord(SSIOTBUF,Ch); /* Enable Transmitter */ _SetEXRegByte(SSIOCON1, SSControl | SSIO_TX_ENAB); /* Wait until Transmit Holding Buffer is empty */ while( !(_GetEXRegByte(SSIOCON1) &...
Page 430 Slave to clear the in-service bit. It is also assumed that the Master is not operating in AEOI, SFNM, or SMM. If the Master were in SMM or SFNM, a Specific EOI would have to be used. On the other hand, if the Master were operating in AEOI mode, no EOI signal would have to be sent.
Page 431 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL None Syntax: Not called by user Real/Protected Mode: No changes required. ******************************************************************************/ void Service_RHBF(void) WORD buffer; buffer = _GetEXRegWord(SSIORBUF); /* Display received character on the screen */ SerialWriteChar(SIO_0, (BYTE)buffer); }/* Service_RHBF */ /***************************************************************************** Service_THBE: Description: Service routine for SSIO interrupts generated by THBE signal.
Page 432 _SetEXRegWord(SSIOTBUF, value); value++; else { /* Disable Transmitter and Transmitter interrupts */ for(i=0;i < 4000; i++) { _asm { _SetEXRegByte(SSIOCON1,_GetEXRegByte(SSIOCON1) & 0xcf); // Clear TEN, TIE } /* Service_THBE */ /***************************************************************************** Example Code showing SSIO transfer in which the transmitter is interrupt-driven and the receiver is polled: InitSSIO(SSIO_RX_ENAB | SSIO_TX_ENAB | SSIO_TX_IE, SSIO_TX_MASTR | SSIO_RX_SLAVE, 0xF0, 0);...
Page 434: Chip-Select Unit
CHIP-SELECT UNIT...
Page 436: Overview
The Chip-select Unit (CSU) of the processor can be used to eliminate external address and bus- cycle decoders in your system. The chip-selects generated by this unit can simplify external “glue logic” by providing signals that can be connected directly to the chip-enable inputs of external memory and I/O devices.
Page 437: Csu Upon Reset
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.2 CSU UPON RESET Upon reset of the processor, only the UCS channel is enabled and all other chip-selects are dis- abled. UCS is enabled for the entire memory space of the processor. The UCS region is initialized upon reset with the following settings: •...
Page 438: Channel Address Comparison Logic
15-bit Channel Address bit x Address bit x bit x 15-bit Channel Mask Figure 14-1. Channel Address Comparison Logic The lower address bits are excluded from address comparisons (only 15 bits are compared). For memory addresses which have 26-bit addresses, the minimum channel address block size is 2 Kbytes;...
Page 439: Determining A Channel's Address Block Size
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15-bit Channel Mask Figure 14-2. Determining a Channel’s Address Block Size Any ones that are to the left of the right-most zero determine the number of blocks and the loca- tions where the blocks are repeated. This is best illustrated by the following four examples. The examples assume the channel is configured for memory addresses;...
Page 440 Example 1 This example establishes a single 32-Kbyte address block starting at 1340000H (a 32-Kbyte boundary). In this example, the 15-bit channel address is the starting address of the channel’s ac- tive address block (because there are no 1’s in the channel mask where there are 1’s in the channel address) 15-bit Channel Address 15-bit Channel Mask...
Page 441 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Example 2 This example establishes four 4-Kbyte address blocks starting at 0000000H, 0002000H, 0004000H, and 0006000H (4-Kbyte boundaries). 15-bit Channel Address 15-bit Channel Mask Channel Active Address Because the least-significant 0 in the channel’s mask is in bit position 2, this channel’s active ad- dress block size is 2 = 4 Kbytes.
Page 442 Example 3 This example establishes four 2-Kbyte address blocks starting at 2413000H, 2433000H, 2613000H, and 2633000H. 15-bit Channel Address 15-bit Channel Mask Channel Active Address Because the least-significant 0 in the channel’s mask is in bit position 1, this channel’s active ad- dress block size is 2 = 2 Kbytes.
Page 443 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14-8 Maximum Memory Address 2633800H Active 26337FFH 2633000H 2613FFFH 2613800H Active 26137FFH 2613000H 2433FFFH 2433800H Active 24337FFH 2433000H 2432FFFH 2413800H Active 24137FFH 2413000H...
Page 444 Example 4 This example establishes two 16-Kbyte address blocks starting at 0E08000H and 0E28000H (16- Kbyte boundaries). 15-bit Channel Address 15-bit Channel Mask Channel Active Address Because the least-significant 0 in the channel mask is in bit position 4, this channel’s active ad- dress block size is 2 = 16 Kbytes.
Page 445: System Management Mode Support
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.3.2 System Management Mode Support The processor supports four operating modes: system management mode (SMM), protected, real and virtual-86 mode. In order for a system to operate correctly in SMM, it must meet several re- quirements.
Page 446: Bus Cycle Length Control
14.3.3 Bus Cycle Length Control Each chip-select channel controls how bus cycles to its address block terminate. Each channel can generate up to 31 wait states and then unconditionally terminate or wait for an external bus ready signal to terminate. If the channel is programmed for wait states and to sample external READY#, the external READY# is ignored until the programmed number of wait states has been inserted into the cycle.
Page 447: Bus Cycle Length Adjustments For Overlapping Regions
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Is any channel Wait for smallest number dependent on of all overlapping regions' external wait state values. ready? Wait State READY# Wait for largest number of asserted? all overlapping regions' wait state values. Complete bus cycle. A2392-02 Figure 14-3.
Page 448: Register Definitions
14.4 REGISTER DEFINITIONS Table 14-1 and Table 14-2 list the signals and registers associated with the chip-select unit. There are seven general-purpose chip-select channels (CSn) and one upper chip-select channel (UCS). Upon reset, the UCS is enabled with the entire 64 Mbyte memory address space as its address block.
Page 449: Csu Registers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Expanded Register Address PINCFG 0F826H Pin Configuration: (read/write) Connects the CS6:5# signals to package pins. P2CFG 0F822H Port 2 Configuration: (read/write) Connects the CS4:0# signals to package pins. CS0ADH 0F402H Chip-select High Address: CS1ADH 0F40AH Defines the upper 10 bits of the chip-select channel address.
Page 450: Pin Configuration Register (Pincfg)
14.4.1 Pin Configuration Register (PINCFG) Use PINCFG bits 6 and 4 to connect the CS6# and CS5# signals to package pins. Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit.
Page 451: Port 2 Configuration Register (P2Cfg)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.4.2 Port 2 Configuration Register (P2CFG) Use P2CFG bits 4–0 to connect the CS4:0# signals to package pins. Port 2 Configuration P2CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin.
Page 452: Chip-Select Address Registers
14.4.3 Chip-select Address Registers The Address Register of each chip-select channel defines the address block that the channel re- sponds to during an access. The value in this register is compared to A25:11 of the processor bus during a memory access and to A15:1 during an I/O access. A bus cycle whose address matches the non-masked (see “Chip-select Mask Registers”...
Page 453: Chip-Select Low Address Register (Cs N Adl, Ucsadl)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Chip-select Low Address CS n ADL ( n = 0–6), UCSADL (read/write) — — Number Mnemonic 15–11 CA5:1 Chip-select Address Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit address. The address bits CA5:1 and the mask bits CM5:1 form a masked address that is compared to memory address bits A15:11 or I/O address bits A5:1.
Page 454: Chip-Select Mask Registers
14.4.4 Chip-select Mask Registers The Mask Register of each chip-select region is used to prevent bits from being compared with the starting address, thus masking them from the comparison. This masking allows you to specify the size of the region being defined. The mask should be set such that it masks the lower address bits being compared, up to the size that you would like the block to be.
Page 455: Chip-Select Low Mask Registers (Cs N Mskl, Ucsmskl)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Chip-select Low Mask CS n MSKL ( n = 0–6), UCSMSKL (read/write) — — — Number Mnemonic 15–11 CM5:1 Chip-select Mask Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit mask. The mask bits CM5:1 and the address bits CA5:1 form a masked address that is compared to memory address bits A15:11 or I/O address bits A5:1.
Page 456: Design Considerations
14.5 DESIGN CONSIDERATIONS When designing with the CSU, consider the following: • Upon reset, UCS# is configured as a 16-bit chip-select signal. If the Boot device is only an 8-bit device, then BS8# must be asserted whenever UCS# is active (until the UCS channel can be reprogrammed to reflect an 8-bit region).
Page 457: Programming Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 14.6 PROGRAMMING CONSIDERATIONS When programming the CSU, consider the following: • When programming a chip-select channel, always program the Low Mask Register last. This ensures that all other bits are properly programmed before the region is enabled. When reprogramming the channel, always disable the channel before changing anything else.
Page 458 Assumptions: REMAPCFG register has Expanded I/O space access enabled (ESE bit set). void Init_CSU(void) _SetEXRegWord(UCSADL, 0x700); _SetEXRegWord(UCSADH, 0x0); _SetEXRegWord(UCSMSKL, 0xFC01); _SetEXRegWord(UCSMSKH, 0x7); _SetEXRegWord(CS4ADL, 0x300); _SetEXRegWord(CS4ADH, 0x8); _SetEXRegWord(CS4MSKL, 0xF801); _SetEXRegWord(CS4MSKH, 0x7); /* Configure the upper chip select */ /* Configure chip select 4 */ CHIP-SELECT UNIT 14-23...
Page 460: Refresh Control Unit
REFRESH CONTROL UNIT...
Page 462: Dynamic Memory Control
The Refresh Control Unit (RCU) simplifies the interface between the processor and a dynamic random access memory (DRAM) device by providing a way to generate periodic refresh requests and refresh addresses. These refresh requests and addresses can then be used by an external DRAM controller to generate the appropriate DRAM signals and addresses needed to perform refresh operations.
Page 463: Refresh Control Unit Overview
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The RAS#-only method requires that the DRAM controller activate its RAS# signal when the RCU activates its REFRESH# signal. This causes the controller to drive the refresh address gen- erated by the RCU onto the DRAM address inputs, refreshing the specified DRAM row. With this method, the controller need not assert the CAS# signal whenever the REFRESH# signal is active.
Page 464: Refresh Control Unit Connections
Processor Clock (CLK2/2) A25:14 A13:1 Figure 15-1. Refresh Control Unit Connections REFRESH CONTROL UNIT Interval Timer Unit Refresh Clock Interval Register 10-bit Interval Counter Timeout Control Unit Refresh Control Register Address Generation Unit Refresh Base Address Register 13-bit Address Counter Refresh Address Register REFRESH# (pin mux)
Page 465: Rcu Signals
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.2.1 RCU Signals Table 15-1 describes the signals associated with the RCU. Device Pin or Internal Signal Signal CLKOUT Device Pin (from Clock and Power Management Unit) Timeout Internal signal (from the interval counter to the control unit) REFRESH# Device pin...
Page 466: Bus Arbitration
The 13-bit address counter is a combination of a binary counter and a 7-bit linear-feedback shift register. The binary counter produces address bits A13:8 and the linear-feedback shift register produces address bits A7:1. The shift register nonsequentially produces all 128 (2 binations.
Page 467: Register Definitions
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.4 REGISTER DEFINITIONS Table 15-2 provides an overview of the registers associated with the RCU. The following sections provide specific programming information for each register. Expanded Register Address RFSCIR 0F4A2H Refresh Clock Interval: (read/write) Determines the processor clock (CLK2/2) count between refresh requests.
Page 468: Refresh Clock Interval Register (Rfscir)
15.4.1 Refresh Clock Interval Register (RFSCIR) Use RFSCIR to program the interval timer unit’s 10-bit down counter. The refresh counter value is a function of DRAM specifications and processor frequency as follows: DRAM refresh period ( s) counter value ---------------------------------------------------------------------------------------------------------------------------------------- - where X = 128 or the # of DRAM rows, whichever is greater.
Page 469: Refresh Control Register (Rfscon)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.4.2 Refresh Control Register (RFSCON) Use RFSCON to enable and disable the refresh control unit and to check the current interval counter value. Refresh Control RFSCON (read/write) — — Number Mnemonic Refresh Control Unit Enable: This bit enables or disables the refresh control unit.
Page 470: Refresh Base Address Register (Rfsbad)
15.4.3 Refresh Base Address Register (RFSBAD) Use RFSBAD to set up the memory region that needs refreshing. The value written to this register forms the upper bits (A25:14) of the refresh address. The RFSBAD register can be used in con- junction with the Chip Select Unit (CSU) to generate a chip-select for the DRAM region during refresh cycles.
Page 471: Refresh Address Register (Rfsadd)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 15.4.4 Refresh Address Register (RFSADD) RFSADD contains the bits A13:1 of the refresh address. The lowest address bit is not used be- cause most DRAM devices contain word-wide memory arrays; for all refresh operations, the low- est address bit remains set.
Page 472: Design Considerations
15.5 DESIGN CONSIDERATIONS Consider the following when programming the RCU. • The system address bus does not contain an address A0 signal; instead, it uses the BLE# and the BHE# pins to generate the lowest address bit. During all refresh operations, BLE# and BHE# are driven high.
Page 473 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • If the counter value stored in the Refresh Clock Interval Register (RFSCIR) is <8 and the RCU is enabled, the RCU always has bus control and other devices will never gain access to the bus. This is because refresh requests have the highest priority in the bus arbitration scheme and you are requesting the bus too often.
Page 474: Ras# Only Refresh Logic: Paged Mode
Upper Address REFRESH# BHE# Intel386™ EX CS n # Embedded Processor BLE# Lower Address Note: A single mux can be used in place of the row and column address buffers. Figure 15-7. RAS# Only Refresh Logic: Paged Mode Non-page Mode In non-paged mode, the row address buffer can be connected to the lower address lines and the column address buffer to the upper lines.
Page 475: Programming Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Lower Address REFRESH# BHE# Intel386™ EX CS n # Embedded Processor BLE# Upper Address Note: A single mux can be used in place of the row and column address buffers. Figure 15-8. RAS# Only Refresh Logic: Non-Paged Mode 15.6 PROGRAMMING CONSIDERATIONS REFRESH# and CS6# share a package pin.
Page 476 Parameters: Counter_Value Value of the refresh interval Returns: Error Codes: E_BADVECTOR User input an invalid parameter E_OK Executed correctly Assumptions: None Syntax: #define REFRESH_INTERVAL int error_code; error_code = InitRCU(REFRESH_INTERVAL); Real/Protected Mode: No changes required *****************************************************************************/ extern int InitRCU(WORD Counter_Value) /* Check that Counter_Value is 10 bits in length */ if (Counter_Value != (Counter_Value &...
Page 477 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Parameters: None Returns: Refresh Interval Counter Value Assumptions: NONE Syntax: WORD CounterValue; CounterValue = Get_RCUCounterValue(); Real/Protected Mode: No changes required ******************************************************************************/ extern WORD Get_RCUCounterValue(void) WORD Counter_Value; Counter_Value = _GetEXRegWord(RFSCON) & 0x3ff; // Counter value contained return(Counter_Value);...
Page 478: Input/Output Ports
INPUT/OUTPUT PORTS...
Page 480: Overview
Input/Output (I/O) ports allow you to transfer information between the processor and the sur- rounding system circuitry. I/O ports are typically used to read system status, monitor system op- eration, output device status, configure system options, and generate control signals. The Intel386™...
Page 481: Port Functionality
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Internal Peripherals Figure 16-1. I/O Port Block Diagram 16.1.1 Port Functionality The function of a bi-directional port pin is controlled by the state of the Port Control Latch (Pn- LTC). This is shown in Figure 16-2. 16-2 P n CFG.
Page 482: Logic Diagram Of A Bi-Directional Port
From Internal Peripheral Read Port Data latch P n LTC Write Port Data Latch Read Port Pin State To Internal Peripheral P n DIR Internal Data Bus (F-Bus) Write Port Direction Read Port Direction From Internal Peripheral Direction P n CFG Control Write Port Control...
Page 483 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The output of the Pin Configuration latch (PnCFG) selects whether the I/O port or peripheral is connected to the pin. When the port is programmed to act as a peripheral pin, both the data for the pin and the directional control signal for the pin come from the associated integrated periph- eral.
Page 484: Pin Multiplexing
Table 16-1. Pin Multiplexing Port Pin Reset Status P1.0 wk 1 P1.1 wk 1 P1.2 wk 1 P1.3 wk 1 P1.4 wk 1 P1.5 wk 1 P1.6 wk 0 P1.7 wk 0 P2.0 wk 1 P2.1 wk 1 P2.2 wk 1 P2.3 wk 1 P2.4...
Page 485: Register Definitions
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 16.2 REGISTER DEFINITIONS Each port has three control registers and a status register associated with it (Table 16-2). The con- trol registers (PnCFG, PnDIR, and PnLTC) can be both read and written. The status register (Pn- PIN) can only be read.
Page 486: Pin Configuration
16.2.1 Pin Configuration You select the operating mode of each pin by writing to the associated bit in the PnCFG registers (Figure 16-3 gives an abbreviated version of these registers; for the complete register descrip- tions, see Appendix D). Setting a bit selects peripheral mode; clearing a bit selects I/O mode. In- ternal peripherals control pins configured for peripheral mode, while the PnDIR (Figure 16-4) and PnLTC (Figure 16-5) registers control pins configured for I/O mode.
Page 487: Port Direction Register (P N Dir)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Port DIrection P n DIR ( n =1–3) (read/write) Number Mnemonic 7–0 PD7:0 Pin Direction: 0 = Configures the pin as a complementary output. 1 = Configures the pin as an open-drain output or high-impedance input. Figure 16-4.
Page 488: Port Pin State Register (P N Pin)
Port Pin State P n PIN ( n =1–3) (read only) Number Mnemonic 7–0 PS7:0 Pin State: Reading a PS bit returns the logic state present on the associated port pin. Figure 16-6. Port Pin State Register (P n PIN) INPUT/OUTPUT PORTS Expanded Addr: ISA Addr:...
Page 489: Initialization Sequence
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 16.2.2 Initialization Sequence After a device reset, a weak pull-up or pull-down resistor holds each pin high or low until user software writes to the PnCFG register. The pins are configured as inputs in I/O port mode. To en- sure that the pins are initialized correctly and that the weak resistors are turned off, follow this suggested initialization sequence.
Page 490: Programming Considerations
16.4 PROGRAMMING CONSIDERATIONS 16.4.1 I/O Ports Code Example The following code example contains a software routine that initializes the I/O port pins. See Ap- pendix C for the included header files. #include <conio.h> #include “80386ex.h” #include “ev386ex.h” /******************************************************************************* Init_IOPorts: Description: This function initializes the direction and mode of the I/O port pins.
Page 491 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define CS2 #define CS3 #define CS4 #define RXD0 #define TXD0 #define CTS0 // Port 3 configuration defines #define TMROUT0 #define TMROUT1 #define INT0 #define INT1 #define INT2 #define INT3 #define PWRDWN #define COMCLK // Port Direction defines #define P0_IN #define P1_IN #define P2_IN...
Page 492 /* Select pin values */ _SetEXRegByte(P1LTC, PortLtc1); _SetEXRegByte(P2LTC, PortLtc2); _SetEXRegByte(P3LTC, PortLtc3); /* Select pin directions */ _SetEXRegByte(P1DIR, PortDir1); _SetEXRegByte(P2DIR, PortDir2); _SetEXRegByte(P3DIR, PortDir3); /* Turn off weak resistors and select either I/O or peripheral mode */ _SetEXRegByte(P1CFG, Port1); _SetEXRegByte(P2CFG, Port2); _SetEXRegByte(P3CFG, Port3); } /* Init_IOPorts */ INPUT/OUTPUT PORTS 16-13...
Page 494: Watchdog Timer Unit
WATCHDOG TIMER UNIT...
Page 496: Overview
The watchdog timer (WDT) unit can function as a general-purpose timer, a software watchdog timer, or a bus monitor, or it can be disabled. This chapter is organized as follows: • Overview (see below) • Watchdog Timer Unit Operation (page 17-3) •...
Page 497: Watchdog Timer Unit Connections
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL READY#). In bus monitor mode, the ADS# signal from the bus interface unit (BIU) reloads the down-counter and the READY# signal stops it. The READY# signal can be generated either ex- ternally or internally, using the WDTRDY bit in the PWRCON register (Figure 17-5). If this bit is deasserted, then an external READY# is required to terminate the cycle when the WDT times out (WDTOUT is asserted) in Bus Monitor mode.
Page 498: Wdt Signals
17.1.1 WDT Signals Table 17-1 describes the signals associated with the WDT. Device Pin or Signal Internal Signal ADS# Device pin IDLE Internal signal READY# Device pin WDTOUT Device pin 17.2 WATCHDOG TIMER UNIT OPERATION After a device reset, the WDT begins counting down in general-purpose timer mode. Unless you change the mode, change the reload value, or disable it, the WDT times out and asserts WDTOUT after 4 million (2 ) processor clock cycles (PH1 or CLKOUT cycles).
Page 499: Idle And Powerdown Modes
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL The reload registers hold a user-defined value that reloads the down-counter when one of the fol- lowing reload events occurs: • In watchdog mode, when system software executes a specific instruction sequence (called a lockout sequence) to the WDTCLR location •...
Page 500: Software Watchdog Mode
17.2.3 Software Watchdog Mode In software watchdog mode, system software must periodically reload the down-counter with a reload value or the timer expires and asserts WDTOUT. The reload value depends on the design of the system software. In general, determining the proper reload value requires software analysis and some experimentation.
Page 501: Disabling The Wdt
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • To change the reload value, write the new values to the WDTRLDH and WDTRLDL registers, as described in steps 1 and 2 above. • To disable or enable bus monitor mode, write to the bus monitor bit (BUSMON): —...
Page 502: Register Definitions
17.4 REGISTER DEFINITIONS This section describes the registers associated with the WDT, and explains how these registers can be used to enable and use each WDT mode. Table 17-2 describes the registers associated with the WDT. Register Address WDTCLR 0F4C8H Watchdog Timer Clear: Write the lockout sequence to this location.
Page 503: Wdt Counter Value Registers (Wdtcnth And Wdtcntl)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL WDT Counter Value (High) WDTCNTH (read only) WC31 WC30 WC29 WC23 WC22 WC21 WDT Counter Value (Low) WDTCNTL (read only) WC15 WC14 WC13 Bit Number Mnemonic High 15–0 WC31:16 WDT Counter Value High Word and Low Word: Read the high word of the counter value from WDTCNTH and the low Low 15–0 WC15:0...
Page 504: Wdt Status Register (Wdtstatus)
WDT Status WDTSTATUS (read/write) WDTEN — — Number Mnemonic WDTEN Watchdog Mode Enabled: This read-only bit indicates whether watchdog mode is enabled. Only a lockout sequence can set this bit and only a device reset can clear it. 0 = Watchdog mode disabled 1 = Watchdog mode enabled 6–2 —...
Page 505: Wdt Reload Value Registers (Wdtrldh And Wdtrldl)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL WDT Reload Value (High) WDTRLDH (read/write) WR31 WR30 WR29 WR23 WR22 WR21 WDT Reload Value (Low) WDTRLDL (read/write) WR15 WR14 WR13 Number Mnemonic High 15–0 WR31:16 WDT Reload Value (High Word and Low Word): Write the high word of the reload value to WDTRLDH and the low word Low 15–0 WR15:0...
Page 506: Power Control Register (Pwrcon)
Power Control Register PWRCON (read/write) — — — Number Mnemonic 7–4 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. WDTRDY Watch Dog Timer Ready: 0 = An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode.
Page 507: Design Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 17.5 DESIGN CONSIDERATIONS This section outlines design considerations for the watchdog timer unit. Depending on the system configuration, a WDT timeout can cause a maskable interrupt, a non- maskable interrupt, or a system reset. Maskable interrupt The WDT timeout signal is internally inverted and connected to the interrupt control unit’s slave IR7 line.
Page 508 See Appendix C for included header files. #include <dos.h> #include <conio.h> #include “80386ex.h” #include “ev386ex.h” /***************************************************************************** ReLoadDownCounter: Description: This function initiates a lockout sequence which results in the setting of the WDTEN bit in the status register. By setting WDTEN, the software watchdog mode is enabled. Parameters: None Returns:...
Page 509 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Parameters: None Returns: 16-bit down-counter value Assumptions: None Syntax: WORD counter_value; counter_value = GetWDT_Count(); Real/Protected Mode: No changes required. ******************************************************************************/ DWORD GetWDT_Count(void) WORD LowWord, HiWord; LowWord = _GetEXRegWord(WDTCNTL); HiWord = _GetEXRegWord(WDTCNTH); return (((DWORD)HiWord << 16) + LowWord); }/* GetWDT_Count */ /***************************************************************************** WDT_BusMonitor:...
Page 510 WDT_BusMonitor(Enable); Real/Protected Mode: No changes required. ******************************************************************************/ void WDT_BusMonitor(BYTE EnableDisable) BYTE Status; Status = _GetEXRegByte(WDTSTATUS); if(EnableDisable) _SetEXRegByte(WDTSTATUS, Status | BIT1MSK); else /* else, Disable */ _SetEXRegByte(WDTSTATUS, Status & ~BIT1MSK); }/* WDT_BusMonitor */ /***************************************************************************** EnableWDTInterrupt: Description: Enables a maskable interrupt on the assertion of WDTOUT Parameters: None Returns:...
Page 511 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Enable8259Interrupt(IR2,IR7); _enable(); /* Enable Interrupts */ } /* EnableWDTInterrupt */ /***************************************************************************** wdtISR: Description: Interrupt Service Routine for Watchdog Timer Parameters: None Returns: None Assumptions: None Syntax: Not called by user; Interrupt Control Unit executes this routine upon acknowledgment of a WDT interrupt Real/Protected Mode: No changes required...
Page 512: Jtag Test-Logic Unit
JTAG TEST-LOGIC UNIT...
Page 514: Overview
The JTAG test-logic unit enables you to test both the device logic and the interconnections be- tween the device and the board (system) it is plugged into. The term JTAG refers to the Joint Test Action Group, the IEEE technical subcommittee that developed the testability standard published as Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture its supplement, Standard 1149.1a-1993.
Page 515: Test Logic Unit Connections
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL • Place all device output pins into their inactive drive (high-impedance) state, allowing external hardware to drive connections that the processor normally drives The test-logic unit (Figure 18-1) is fully compliant with IEEE Standard 1149.1. It consists of the test access port (TAP), the test access port controller, the instruction register (IR), and three data registers (IDCODE, BYPASS, and BOUND).
Page 516: Test Access Port Dedicated Pins
18.2 TEST-LOGIC UNIT OPERATION 18.2.1 Test Access Port (TAP) The test access port consists of five dedicated pins (four inputs and one output). It is through these pins that all communication with the test-logic unit takes place. This unit has its own clock (TCK) and reset (TRST#) pins, so it is independent of the rest of the device.
Page 517: Test Access Port (Tap) Controller
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.2.2 Test Access Port (TAP) Controller The TAP controller is a finite-state machine that is capable of 16 states (Figure 18-2). Three of its states provide the basic actions required for testing: • Applying stimulus (update-data-register) •...
Page 518: Example Tap Controller State Selections
Table 18-2. TAP Controller State Descriptions (Sheet 2 of 2) State Test-logic is idle and the instruction register retains Select-IR-Scan its previous state. Loads the SAMPLE/PRELOAD instruction Capture-IR instruction (0001) into the instruction register. Shifts the SAMPLE/PRELOAD instruction one Shift-IR stage toward TDO while shifting the new instruction in from TDI on each rising edge of TCK.
Page 519: Tap Controller (Finite-State Machine)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Test - Logic - Reset Run - Test/ Idle Figure 18-2. TAP Controller (Finite-State Machine) 18-6 Select - Select - DR - Scan IR - Scan Capture - Capture - Shift - Shift - Exit1 - Exit1 - Pause -...
Page 520: Instruction Register (Ir)
18.2.3 Instruction Register (IR) An instruction opcode is clocked serially through the TDI pin into the four-bit instruction register (Figure 18-3). The instruction determines which data register is affected. Table 18-4 lists the in- structions with their binary opcodes, descriptions, and associated registers. Instruction Register Number Mnemonic...
Page 521: Data Registers
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.2.4 Data Registers The test-logic unit uses three data registers: bypass, identification code, and boundary-scan. The instruction determines which data register is used. The single-bit bypass register (BYPASS) provides a minimal-length serial path between TDI and TDO.
Page 522: Boundary-Scan Register Bit Assignments
The boundary-scan register (BOUND) holds data to be applied to the pins or data observed at the pins. Each bit corresponds to a specific pin (Table 18-5). Table 18-5. Boundary-scan Register Bit Assignments M/IO# D/C# W/R# READY# BS8# BLE# BHE# ADS# P3.0/TMROUT0/ P3.1/TMROUT1/...
Page 523: Testing
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.3 TESTING This section explains how to use the test-logic unit to test the device and the board interconnec- tions. For any test, you must load an instruction and perform an instruction-scan cycle, then sup- ply the correct sequence of ones and zeros to move the TAP controller through the required states to perform the test.
Page 524: Disabling The Output Drivers
JTAG TEST-LOGIC UNIT Typically, you would use the SAMPLE/PRELOAD instruction to load data onto the boundary- scan register’s latched parallel outputs before loading the EXTEST instruction. You load the EX- TEST instruction by manipulating TDI to supply the binary opcode (0000). The Update-DR state drives the preloaded data onto the pins for the first test.
Page 525: Timing Information
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.4 TIMING INFORMATION The test-logic unit’s input/output timing is as specified in IEEE 1149.1. Figure 18-5 shows the pin timing associated with loading the instruction register and Figure 18-6 shows the timing for loading a given data register. Controller State Data Input to IR IR Shift-Register...
Page 526: Internal And External Timing For Loading A Data Register
Controller State Data Input to IR IR Shift-Register Parallel Output of IR Data Input to TDR TDR Shift-Register Parallel Output of TDR Instruction Register Inactive Active TDO Enable Figure 18-6. Internal and External Timing for Loading a Data Register Instruction Old Data Test Data Register Active...
Page 527: Design Considerations
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 18.5 DESIGN CONSIDERATIONS This section outlines considerations for the test-logic unit. • The JTAG Test-Logic Unit must be reset upon power-up using the TRST# pin. (To do this, invert the RESET signal and send this inverted RESET to the TRST# pin). If this is not done, the processor may power-up with the JTAG test-logic unit in control of the device pins, and the system does not initialize properly.
Page 528: Signal Descriptions
SIGNAL DESCRIPTIONS...
Page 530: Appendix Asignal Descriptions
This appendix provides reference information for the pins and signals of the device, including the states of certain pins during reset, idle, powerdown, and hold. The information is presented in four tables: • Table A-1 defines the abbreviations used in Table A-2 to describe the signals. •...
Page 531 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-2 is an alphabetical list of the signals available at the device pins. The Multiplexed With column lists other signals that share a pin with the signal listed in the Signal column. Table A-2. Description of Signals Available at the Device Pins (Sheet 1 of 6) Signal Type A25:19...
Page 532 Table A-2. Description of Signals Available at the Device Pins (Sheet 2 of 6) Signal Type CTS1# Clear to Send: CTS0# Indicates that the modem or data set is ready to exchange data with the SIO channel. D15:0 Data Bus: Inputs data during memory read, I/O read, and interrupt acknowledge cycles;...
Page 533 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-2. Description of Signals Available at the Device Pins (Sheet 3 of 6) Signal Type HOLD Hold Request: An external bus master asserts HOLD to request control of the local bus. The processor finishes the current nonlocked bus transfer, releases the bus signals, and asserts HLDA.
Page 534 Table A-2. Description of Signals Available at the Device Pins (Sheet 4 of 6) Signal Type P2.7 Port 2: P2.6 General-purpose, bidirectional I/O port. P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.7 Port 3: P3.6 General-purpose, bidirectional I/O port. P3.5 P3.4 P3.3 P3.2 P3.1...
Page 535 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-2. Description of Signals Available at the Device Pins (Sheet 5 of 6) Signal Type SMI# System Management Interrupt: Causes the device to enter System Management Mode. SMI# is the highest priority external interrupt. SMIACT# System Management Interrupt Active: Indicates that the processor is in System Management...
Page 536 Table A-2. Description of Signals Available at the Device Pins (Sheet 6 of 6) Signal Type Test Mode Select: Controls the sequence of the test-logic unit’s TAP controller states. Sampled on the rising edge of TCK. TRST# Test Reset: Resets the test-logic unit’s TAP controller. Asynchronously clears the data registers and initializes the instruction register to 0010 (the IDCODE instruction opcode).
Page 537 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-3 defines the abbreviations used in Table A-4 to describe the pin states. Table A-3. Pin State Abbreviations Abbreviation Description Output driven to V Output driven to V Output floats Output remains active Output retains current state Pin floats and has a temporary weak pull-up...
Page 538 Table A-4 lists the states of output and bidirectional pins after reset and during idle mode, pow- erdown, and hold. Table A-4. Pin States After Reset and During Idle, Powerdown, and Hold (Sheet 1 of 2) Symbol Type A25:1 ADS# BHE# BLE# CAS2:0...
Page 539 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table A-4. Pin States After Reset and During Idle, Powerdown, and Hold (Sheet 2 of 2) STXCLK TMROUT2 TMROUT1:0 TXD1 TXD0 UCS# WDTOUT W/R# NOTES: X if clock source is internal; Q if clock source is external. Q when shifting data out through the JTAG port, otherwise Z.
Page 540: Compatibility With The Pc/At* Architecture
COMPATIBILITY WITH THE PC/AT* ARCHITECTURE...
Page 542: B.1.1 Dma Unit
COMPATIBILITY WITH THE PC/AT* The Intel386™ EX embedded processor is NOT 100% PC/AT* compatible. Due to compatibility issues, not all PC software executes on the Intel386 EX processor. In addition, not all ISA/PC- 104 cards operate in an Intel386 EX processor system. It is the responsibility of the designer to determine if a specific PC/AT software or hardware pack- age operates on an Intel386 EX processor system.
Page 543: Industry Standard Bus (Isa) Signals
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL To eliminate these problems with an 8237A DMA controller, the Intel386 EX processor inte- grates a DMA controller unit that differs from the 8237A DMA in these ways: • It provides two channels, each capable of either byte or word transfers. •...
Page 544: B-2 Derivation Of Aen Signal For Intel386™ Ex Processor-Based Systems
HLDA Processor Figure B-1. Derivation of AEN Signal in a Typical PC/AT System For systems based on Intel386 EX processor, the AEN signal could be derived as shown in Figure B-2. Notice that since the DMA acknowledge signals are used instead of a generic HLDA, there is no need to incorporate the REFRESH# signal in the logic.
Page 545: B.1.4 Sio Units
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL the Intel386 EX embedded processor) demonstrates the design of a Synchronous Expansion Bus that is very similar to the ISA bus. The Intel386 EX processor is not capable of providing a 100% compatible ISA bus due to its lack of DMA channels and interrupt inputs. B.1.3 Interrupt Control Unit Interrupt signals IRQ10, IRQ11, and IRQ15 found on an ISA bus are not directly available for...
Page 546: B.2 Software Considerations For A Pc/At System Architecture
(APM), Source, Remote Floppy, OEM Configurable, and Video/Keyboard rerouted through the serial port. For a complete list of vendors and their features, call the Intel BBS as described in “Electronic Support Systems” on page 1-6. A good evaluation vehicle is the EV386EX Evalua- tion Board which comes with five different third party BIOS demonstrations.
Page 548: Example Code Header Files
EXAMPLE CODE HEADER FILES...
Page 550: Register Definitions For Code Examples
This appendix contains the header files called by the code examples that are included in several chapters of this manual. Section C.1 contains the register definitions for each code routine. Sec- tion C.2 contains the variable definitions. REGISTER DEFINITIONS FOR CODE EXAMPLES 80386EX REGISTER DEFINITIONS */ #define _SetEXRegWord(reg,val) #define _SetEXRegByte(reg,val)
Page 551 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define OCW2SDOS 0x00A0 #define OCW3MDOS 0x0020 #define OCW3SDOS 0x00A0 /* CONFIGURATION Registers */ #define DMACFG 0xF830 #define INTCFG 0xF832 #define TMRCFG 0xF834 #define SIOCFG 0xF836 #define P1CFG 0xF820 #define P2CFG 0xF822 #define P3CFG 0xF824 #define PINCFG 0xF826 /* WATCHDOG TIMER Registers */...
Page 552 #define IIR0 0xF4FA #define LCR0 0xF4FB #define MCR0 0xF4FC #define LSR0 0xF4FD #define MSR0 0xF4FE #define SCR0 0xF4FF /* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */ #define RBR0DOS 0x03F8 #define THR0DOS 0x03F8 #define TBR0DOS 0x03F8 #define DLL0DOS 0x03F8 #define IER0DOS 0x03F9 #define DLH0DOS...
Page 553 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define SSIOCON2 0xF488 #define SSIOCTR 0xF48A /* CHIP SELECT UNIT Registers */ #define CS0ADL 0xF400 #define CS0ADH 0xF402 #define CS0MSKL 0xF404 #define CS0MSKH 0xF406 #define CS1ADL 0xF408 #define CS1ADH 0xF40A #define CS1MSKL 0xF40C #define CS1MSKH 0xF40E #define CS2ADL 0xF410...
Page 554 #define DMACMD1 0xF008 #define DMASTS 0xF008 #define DMASRR 0xF009 #define DMAMSK 0xF00A #define DMAMOD1 0xF00B #define DMACLRBP 0xF00C #define DMACLR 0xF00D #define DMACLRMSK 0xF00E #define DMAGRPMSK 0xF00F #define DMA0REQL 0xF010 #define DMA0REQH 0xF011 #define DMA1REQL 0xF012 #define DMA1REQH 0xF013 #define DMABSR 0xF018 #define DMACHR 0xF019...
Page 555: C.2 Example Code Defines
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL EXAMPLE CODE DEFINES /*********************** Global typedef **********************/ typedef unsigned char BYTE; typedef unsigned short WORD; typedef unsigned long DWORD; /******************** Global Used defines ********************/ /* Error Flags */ #define E_OK #define E_INVALID_DEVICE #define E_INVALID_VECTOR #define E_BADVECTOR #define INTERRUPT_ISR #define TRAP_ISR...
Page 556 #define MPIN_INT0 #define MPIN_INT1 #define MPIN_INT2 #define MPIN_INT3 /* ICU Master External Cascade IRs */ #define MCAS_IR1 #define MCAS_IR2 #define MCAS_IR5 #define MCAS_IR6 #define MCAS_IR7 /* ICU Slave Pins */ #define SPIN_INT4 #define SPIN_INT5 #define SPIN_INT6 #define SPIN_INT7 /* ICU IRQ Mask Values*/ #define IR0 #define IR1 #define IR2...
Page 557 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL /************ Asynchronous Serial I/O Port defines ***********/ #define SIO_0 #define SIO_1 #define SIO0_IRQ #define SIO1_IRQ #define SIO_5DATA #define SIO_6DATA #define SIO_7DATA #define SIO_8DATA #define SIO_1STOPBIT #define SIO_2STOPBIT #define SIO_NOPARITY #define SIO_ODDPARITY #define SIO_EVNPARITY #define SIO_FRC0PARITY #define SIO_FRC1PARITY #define SIO_SETBREAK #define SIO_INTERNAL_SRC...
Page 558 #define SIO_TX_EMPTY /* Offsets from beginning of SIO port addresses */ #define RBR #define TBR #define DLL #define IER #define DLH #define IIR #define LCR #define MCR #define LSR #define MSR #define SCR #define SIO0_BASE #define SIO1_BASE /* Define Function Macros */ #define GetSIO0Status() #define GetSIO1Status() #define GetSIO0InterruptID()
Page 559 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL typedef enum DMA_Channel0 = 0, DMA_Channel1 = 1 } DMAChannelEnum; typedef enum ERR_NONE = 0, ERR_BADINPUT = -1 } ERREnum; /* DMA Function Definitions */ int SetDMAReqIOAddr(int nChannel, WORD wIO); int SetDMATargMemAddr(int nChannel, void *ptMemory); int SetDMAXferCount(int nChannel, DWORD lCount);...
Page 560 #define P1_IN #define P2_IN #define P3_IN #define P4_IN #define P5_IN #define P6_IN #define P7_IN #define Px_OUT /* Pin configuration defines */ #define RTS1 #define SSIOTX #define DTR1 #define SRXCLK #define TXD1 #define DACK1 #define CTS1 #define EOP #define CS5 #define DACK0 #define TIMER2 #define COPROC #define REFRESH...
Page 561 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL #define TMR_GATE_EXTRN #define TMR_OUT_ENABLE #define TMR_OUT_DISABLE #define TMR_ENABLE #define TMR_DISABLE /* Timer Macros Definitions */ #define DisableTimer() \ _SetEXRegByte( TMRCFG, (_GetEXRegByte(TMRCFG) | 0x80)) #define EnableTimer() \ _SetEXRegByte( TMRCFG, (_GetEXRegByte(TMRCFG) & 0x7f)) /* Timer Function Definitions */ extern int InitTimer (int Unit, WORD Mode, BYTE Inputs, BYTE Output, WORD InitCount, int Enable);...
Page 562 BYTE PreScale); extern WORD SSerialReadWord(BYTE MasterSlave); extern void SSerialWriteWord(WORD Ch,BYTE MasterSlave); void interrupt far SSIO_ISR(void); extern void Service_RHBF(void); extern void Service_THBE(void); /********************* Watch Dog Timer ***********************/ #define SetWatchDogReload(ReloadHi,ReloadLow) \ _SetEXRegWord(WDTRLDL,ReloadLow);_SetEXRegWord(WDTRLDH,ReloadHi); #define WatchDogClockDisable()\ _SetEXRegByte(WDTSTATUS, _GetEXRegByte(WDTSTATUS) | BIT0MSK) #define WatchDogClockEnable()\ _SetEXRegByte(WDTSTATUS, _GetEXRegByte(WDTSTATUS) & ~BIT0MSK) /* Watch Dog Timer Function Definitions */ extern void ReLoadDownCounter(void);...
Page 564: System Register Quick Reference
SYSTEM REGISTER QUICK REFERENCE...
Page 566: Peripheral Register Addresses
SYSTEM REGISTER QUICK REFERENCE PERIPHERAL REGISTER ADDRESSES Table D-1. Peripheral Register Addresses (Sheet 1 of 6) Expanded PC/AT Address Address F000H 0000H F001H 0001H F002H 0002H F003H 0003H F004H 0004H F005H 0005H F006H 0006H F007H 0007H F008H 0008H F009H 0009H F00AH 000AH F00BH...
Page 567 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table D-1. Peripheral Register Addresses (Sheet 2 of 6) Expanded PC/AT Address Address F019H F01AH F01BH F01CH F01DH F01EH F020H 0020H F021H 0021H 0022H 0022H F040H 0040H F041H 0041H F042H 0042H F043H 0043H F080H F081H 0081H F082H...
Page 568 Table D-1. Peripheral Register Addresses (Sheet 3 of 6) Expanded PC/AT Address Address F08EH F08FH F098H F099H F09AH F09BH F092H 0092H F0A0H 00A0H F0A1H 00A1H F400H F402H F404H F406H F408H F40AH F40CH F40EH F410H F412H F414H F416H F418H F41AH F41CH F41EH F420H F422H...
Page 569 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table D-1. Peripheral Register Addresses (Sheet 4 of 6) Expanded PC/AT Address Address F426H F428H F42AH F42CH F42EH F430H F432H F434H F436H F438H F43AH F43CH F43EH F480H F482H F484H F486H F488H F48AH F4A0H F4A2H F4A4H F4A6H F4C0H...
Page 570 Table D-1. Peripheral Register Addresses (Sheet 5 of 6) Expanded PC/AT Address Address Asynchronous Serial I/O Channel 0 (COM1) F4F8H 03F8H F4F9H 03F9H F4FAH 03FAH F4FBH 03FBH F4FCH 03FCH F4FDH 03FDH F4FEH 03FEH F4FFH 03FFH Clock Generation and Power Management F800H F804H Device Configuration Registers...
Page 571 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table D-1. Peripheral Register Addresses (Sheet 6 of 6) Expanded PC/AT Address Address Asynchronous Serial I/O Channel 1 (COM2) F8F8H 02F8H F8F9H 02F9H F8FAH 02FAH F8FBH 02FBH F8FCH 02FCH F8FDH 02FDH F8FEH 02FEH F8FFH 02FFH NOTES: Byte pointer in flip-flop in DMA determines which register is accessed.
Page 572: D.2 Clkprs
CLKPRS Clock Prescale Register CLKPRS (read/write) — — — Number Mnemonic 15–9 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 8–0 PS8:0 Prescale Value: These bits determine the divisor that is used to generate PSCLK. Legal values are from 0000H (divide by 2) to 01FFH (divide by 513).
Page 573: D.3 Cs N Adh (Ucsadh)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CS n ADH (UCSADH) Chip-select High Address CS n ADH (n = 0–6), UCSADH (read/write) — — — CA13 CA12 CA11 Number Mnemonic 15–10 — Reserved; for compatibility with future devices, write zeros to these bits. 9–0 CA15:6 Chip-select Channel Address Upper Bits:...
Page 574: D.4 Cs N Adl (Ucsadl)
CS n ADL (UCSADL) Chip-select Low Address CS n ADL ( n = 0–6), UCSADL (read/write) — — Number Mnemonic 15–11 CA5:1 Chip-select Address Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit address. The address bits CA5:1 and the mask bits CM5:1 form a masked address that is compared to memory address bits A15:11 or I/O address bits A5:1.
Page 575: D.5 Cs N Mskh (Ucsmskh)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL CS n MSKH (UCSMSKH) Chip-select High Mask CS n MSKH ( n = 0–6), UCSMSKH (read/write) — — — CM13 CM12 CM11 Number Mnemonic 15–10 — Reserved; for compatibility with future devices, write zeros to these bits. 9–0 CM15:6 Mask Value Upper Bits:...
Page 576: D.6 Cs N Mskl (Ucsmskl)
CS n MSKL (UCSMSKL) Chip-select Low Mask CS n MSKL ( n = 0–6), UCSMSKL (read/write) — — — Number Mnemonic 15–11 CM5:1 Chip-select Mask Value Lower Bits: Defines the lower 5 bits of the channel’s 15-bit mask. The mask bits CM5:1 and the address bits CA5:1 form a masked address that is compared to memory address bits A15:11 or I/O address bits A5:1.
Page 577: Dll N And Dlh N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DLL n AND DLH n Divisor Latch Low DLL0, DLL1 (read/write) Divisor Latch High DLH0, DLH1 (read/write) UD15 UD14 UD13 Number Mnemonic DLL n LD7:0 Lower 8 Divisor and Upper 8 Divisor Bits: (7–0) Write the lower 8 divisor bits to DLL n and the upper 8 divisor bits to DLH n .
Page 578: D.8 Dmabsr
DMABSR DMA Bus Size DMABSR (write only) — — Number Mnemonic — Reserved; for compatibility with future devices, write zero to this bit. Requester Bus Size: Specifies the requester’s data bus width for the channel specified by bit 0 = 16-bit bus 1 = 8-bit bus —...
Page 579: D.9 Dmacfg
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DMACFG DMA Configuration DMACFG (read/write) D1MSK D1REQ2 D1REQ1 Number Mnemonic D1MSK DMA Acknowledge 1 Mask: 0 = DMA channel 1’s acknowledge (DMAACK1#) signal is not masked. 1 = Masks DMA channel 1’s acknowledge (DMAACK1#) signal. Useful 6–4 D1REQ2:0 DMA Channel 1 Request Connection:...
Page 580: D.10 Dmachr
D.10 DMACHR DMA Chaining DMACHR (write only) — — — Number Mnemonic 7–3 — Reserved; for compatibility with future devices, write zeros to these bits. Chaining Enable: 0 = Disables the chaining buffer-transfer mode for the channel specified 1 = Enables the chaining buffer-transfer mode for the channel specified Must be 0 for correct operation.
Page 581: D.11 Dmacmd1
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.11 DMACMD1 DMA Command 1 DMACMD1 (write only) — — — Number Mnemonic 7–5 — Reserved; for compatibility with future devices, write zeros to these bits. Priority Rotation Enable: 0 = Priority is fixed based on value in DMACMD2. 1 = Enables the rotation method for changing the bus control priority —...
Page 582: D.12 Dmacmd2
D.12 DMACMD2 DMA Command 2 DMACMD2 (write only) — — — Number Mnemonic 7–4 — Reserved; for compatibility with future devices, write zeros to these bits. 3–2 PL1:0 Low Priority Level Set: Use these bits to assign a particular bus request to the lowest priority level in fixed priority mode.
Page 583: D.13 Dmagrpmsk
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.13 DMAGRPMSK DMA Group Channel Mask DMAGRPMSK (read/write) — — — Number Mnemonic 7–2 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. HRM1 Hardware Request Mask 1: 0 = Channel 1’s hardware requests are not masked.
Page 584: D.14 Dmaien
D.14 DMAIEN DMA Interrupt Enable DMAIEN (read/write) — — — Number Mnemonic 7–2 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Transfer Complete 1: 0 = Disables Transfer Complete interrupts. 1 = Connects channel 1’s transfer complete signal to the interrupt Note: When channel 1 is in chaining mode (DMACHR.2=1 and DMACHR.0=1), this bit is a don’t care.
Page 585: D.15 Dmais
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.15 DMAIS DMA Interrupt Status DMAIS (read only) — — Number Mnemonic 7–6 — Reserved. These bits are undefined. Transfer Complete 1: When set, this bit indicates that channel 1 has completed a buffer transfer (either its byte count expired or it received an EOP# input).
Page 586: D.16 Dmamod1
D.16 DMAMOD1 DMA Mode 1 DMAMOD1 (write only) DTM1 DTM0 Number Mnemonic 7–6 DTM1:0 Data-transfer Mode: 00 = Demand 01 = Single 10 = Block 11 = Cascade Target Increment/Decrement: 0 = Causes the target address to be incremented after each data 1 = Causes the target address for the channel specified by bit 0 to be Note: When the target address is programmed to remain constant (DMAMOD2.2 = 1), this bit is a don’t care.
Page 587: D.17 Dmamod2
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.17 DMAMOD2 DMA Mode 2 DMAMOD2 (write only) Number Mnemonic Bus Cycle Option: 0 = Selects the fly-by data transfer bus cycle option for the channel specified 1 = Selects the two-cycle data transfer bus cycle option for the channel Requester Device Type: 0 = Clear this bit when the requester for the channel specified by bit 0 is in 1 = Set this bit when the requester for the channel specified by bit 0 is in I/O...
Page 588: D.18 Dmamsk
D.18 DMAMSK DMA Individual Channel Mask DMAMSK (write only) — — — Number Mnemonic 7–3 — Reserved; for compatibility with future devices, write zeros to these bits. Hardware Request Mask: 0 = Unmasks (enables) hardware requests for the channel specified by 1 = Masks (disables) hardware requests for the channel specified by NOTE: When this bit is set, the channel can still receive software requests.
Page 589: Dma N Byc N, Dma N Req N And Dma N Tar N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.19 DMA n BYC n, DMA n REQ n AND DMA n TAR n Requester Address Target Address Byte Count Requester Address Target Address Byte Count D-24 DMA Channel 0 DMA0REQ3 DMA0REQ2 DMA0REQ1 F011H F011H (BP=1) (BP=0)
Page 590: D.20 Dmaovfe
D.20 DMAOVFE DMA Overflow Enable DMAOVFE (read/write) — — — Number Mnemonic 7–4 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. ROV1 Channel 1 Requester Overflow Enable: 0 = lowest 16 bits of requester address increment/decrement 1 = all bits of requester address increment/decrement TOV1 Channel 1 Target &...
Page 591: D.21 Dmasrr
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.21 DMASRR DMA Software Request (read format) DMASRR — — — Number Mnemonic 7–2 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. Software Request 1: When set, this bit indicates that channel 1 has a software request pending.
Page 592: D.22 Dmasts
D.22 DMASTS DMA Status DMASTS (read only) — — Bit Number Bit Mnemonic 7–6 — Reserved. These bits are undefined. Request 1: When set, this bit indicates that channel 1 has a hardware request pending. When the request is removed, this bit is cleared. Request 0: When set, this bit indicates that channel 0 has a hardware request pending.
Page 593: Icw1 (Master And Slave
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.23 ICW1 (MASTER AND SLAVE) Initialization Command Word 1 ICW1 (master and slave) (write only) Number Mnemonic 7–5 — Clear these bits to guarantee device operation. RSEL1 Register Select 1 (Also see OCW2 and OCW3): ICW1, OCW2, and OCW3 are accessed through the same addresses.
Page 594: D.25 Icw3 (Master)
D.24 ICW2 (MASTER AND SLAVE) Initialization Command Word 2 ICW2 (master and slave) (write only) Number Mnemonic 7–3 T7:3 Base Interrupt Type: Write the base interrupt vector’s five most-significant bits to these bits. 2–0 T2:0 Clear these bits to guarantee device operation. D.25 ICW3 (MASTER) Initialization Command Word 3 ICW3 (master)
Page 595: D.26 Icw3 (Slave)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.26 ICW3 (SLAVE) Initialization Command Word 3 ICW3 (slave) (write only) Number Mnemonic 7–2 — Clear these bits to guarantee device operation. — Set this bit to guarantee device operation. — Clear this bit to guarantee device operation. D.27 ICW4 (MASTER AND SLAVE) Initialization Command Word 4 ICW4 (master and slave)
Page 596: D.28 Idcode
D.28 IDCODE Identification Code Register IDCODE Number Mnemonic 31–28 Device version number. V3:0 27–12 PN15:0 Device part number. 11–1 MFR10:0 Manufacturer identification (compressed JEDEC106-A code). Identification Present. Always true for this device. This is the first data bit shifted out of the device during a data scan immediately following an exit from the test-logic-reset state.
Page 597: Ier N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.29 IER n Interrupt Enable IER0, IER1 (read/write) — — — Number Mnemonic 7–4 — Reserved; for compatibility with future devices, write zeros to these bits. Modem Status Interrupt Enable: 0 = Modem input signal changes do not cause interrupts. 1 = Connects the modem status signal to the interrupt control unit’s Receiver Line Status Interrupt Enable: 0 = LSR error conditions do not cause interrupts.
Page 598: Iir N
D.30 IIR n Interrupt ID IIR0, IIR1 (read only) — — — Number Mnemonic 7–3 — Reserved. These bits are undefined. IS2:1 Interrupt Source: If an interrupt is pending (bit 0 = 0), these bits specify which status signal caused the pending interrupt. * When one of the modem input signals (CTS n #, DSR n #, RI n #, and DCD n #) changes state, the modem status signal is activated.
Page 599: D.31 Intcfg
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.31 INTCFG Interrupt Configuration INTCFG (read/write) Number Mnemonic Cascade Enable: 0 = Disables the cascade signals CAS2:0 from appearing on the A18:16 1 = Enables the cascade signals CAS2:0, providing access to external Internal Master IR3 Connection: See Table 5-1 on page 5-8 for all the IR3 configuration options.
Page 600 D.32 IR Instruction Register Number Mnemonic 3–0 INST3:0 Instruction opcode. At reset (using TRST#, or after 5 TCK cycles with TMS held low), this field is loaded with 0010, the opcode for the IDCODE instruction. Instructions are shifted into this field serially through the TDI pin.
Page 601: Lcr N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.33 LCR n Serial Line Control LCR0, LCR1 (read/write) DLAB Number Mnemonic DLAB Divisor Latch Access Bit: This bit determines which of the multiplexed registers is accessed. 0 = Allows access to the receiver and transmit buffer registers (RBR n and 1 = Allows access to the divisor latch registers (DLL n and DLH n ).
Page 602: Lsr N
D.34 LSR n Serial Line Status LSR0, LSR1 (read only) — Number Mnemonic — Reserved. This bit is undefined. Transmitter Empty: The transmitter sets this bit to indicate that the transmit shift register and transmit buffer register are both empty. Writing to the transmit buffer register clears this bit.
Page 603: Mcr N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.35 MCR n Modem Control MCR0, MCR1 (read/write) — — — Number Mnemonic 7–5 — Reserved; for compatibility with future devices, write zeros to these bits. LOOP Loop Back Test Mode: 0 = Normal mode 1 = Setting this bit puts the SIO n into diagnostic (or loop back test) mode.
Page 604: Msr N
D.36 MSR n Modem Status MSR0, MSR1 (read only) Number Mnemonic Data Carrier Detect: This bit is the complement of the data carrier detect (DCD n #) input. In diagnostic test mode, this bit is equivalent to MCR n .3 (OUT2). Ring Indicator: This bit is the complement of the ring indicator (RI n #) input.
Page 605: Ocw1 (Master And Slave
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.37 OCW1 (MASTER AND SLAVE) Operation Command Word 1 OCW1 (master and slave) (read/write) Number Mnemonic 7–0 M7:0 Mask IR: 0 = Enables interrupts on the corresponding IR signal. 1 = Disables interrupts on the corresponding IR signal. NOTE: Setting the mask bit does not clear the respective interrupt pending bit.
Page 606: Ocw2 (Master And Slave
D.38 OCW2 (MASTER AND SLAVE) Operation Command Word 2 OCW2 (master and slave) (write only) Number Mnemonic The Rotate (R), Specific Level (SL), and End-of-Interrupt (EOI) Bits: These bits change the priority structure and/or send an EOI command. R SL EOI 0 0 0 0 0 1 0 1 0...
Page 607: Ocw3 (Master And Slave
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.39 OCW3 (MASTER AND SLAVE) Operation Command Word 3 OCW3 (master and slave) (write only) ESMM Number Mnemonic — Clear this bit to guarantee device operation. ESMM Enable Special Mask Mode (ESMM) and Special Mask Mode (SMM): Use these bits to enable or disable special mask mode.
Page 608: D.40 P1Cfg
D.40 P1CFG Port 1 Configuration P1CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P1.7 at the package pin. 1 = Selects HLDA at the package pin. Pin Mode: 0 = Selects P1.6 at the package pin. 1 = Selects HOLD at the package pin. Pin Mode: 0 = Selects P1.5 at the package pin.
Page 609: D.41 P2Cfg
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.41 P2CFG Port 2 Configuration P2CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P2.7 at the package pin. 1 = Selects CTS0# at the package pin. Pin Mode: 0 = Selects P2.6 at the package pin. 1 = Selects TXD0 at the package pin.
Page 610: D.42 P3Cfg
D.42 P3CFG Port 3 Configuration P3CFG (read/write) Number Mnemonic Pin Mode: 0 = Selects P3.7 at the package pin. 1 = Selects COMCLK at the package pin. Pin Mode: 0 = Selects P3.6 at the package pin. 1 = Selects PWRDOWN at the package pin. Pin Mode: 0 = Selects P3.5 at the package pin.
Page 611: D.43 Pincfg
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.43 PINCFG Pin Configuration PINCFG (read/write) — Number Mnemonic — Reserved. This bit is undefined; for compatibility with future devices, do not modify this bit. Pin Mode: 0 = Selects CS6# at the package pin. 1 = Selects REFRESH# at the package pin.
Page 612: P N Dir
D.44 P n DIR Port DIrection P n DIR ( n =1–3) (read/write) Number Mnemonic 7–0 PD7:0 Pin Direction: 0 = Configures the pin as a complementary output. 1 = Configures the pin as an open-drain output or high-impedance input. SYSTEM REGISTER QUICK REFERENCE Expanded Addr: ISA Addr:...
Page 613: P N Ltc
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.45 P n LTC Port Data Latch P n LTC ( n =1–3) (read/write) Number Mnemonic 7–0 PL7:0 Port Data Latch: Writing a value to a PL bit causes that value to be driven onto the corresponding pin.
Page 614: Poll (Master And Slave
D.47 POLL (MASTER AND SLAVE) Poll Status Byte POLL (master and slave) (read only) — — Number Mnemonic Interrupt Pending: 0 = No request pending. 1 = Indicates that a device attached to the 82C59A requires servicing. 6–3 — Reserved. These bits are undefined. 2–0 L2:0 Interrupt Request Level:...
Page 615: D.48 Port92
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.48 PORT92 Port 92 Configuration PORT92 (read/write) — — — Number Mnemonic 7–2 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. A20G A20 Grounded: 0 = Clearing this bit forces address line A20 to 0. This bit affects 1 = Setting this bit leaves core-generated addresses unmodified.
Page 616: D.49 Pwrcon
D.49 PWRCON Power Control Register PWRCON (read/write) — — — Number Mnemonic 7–4 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. WDTRDY Watch Dog Timer Ready: 0 = An external READY must be generated to terminate the cycle when 1 = Internal logic generates READY# to terminate the cycle when the HSREADY Halt/Shutdown Ready:...
Page 617: Rbr N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.50 RBR n Receive Buffer RBR0, RBR1 (read only) Number Mnemonic 7–0 RB7:0 Receive Buffer Bits: These bits make up the last word received. The receiver shifts bits in, starting with the least-significant-bit. The receiver then strips off the asynchronous bits (start, parity, and stop) and transfers the received data bits from the receive shift register to the receive buffer.
Page 618: D.51 Remapcfg
D.51 REMAPCFG Address Configuration Register REMAPCFG — — — Number Mnemonic 0 = Disables expanded I/O space 1 = Enables expanded I/O space 14–7 — Reserved. 0 = Makes serial channel 1 (COM2) accessible in both DOS I/O space 1 = Remaps serial channel 1 (COM2) address into expanded I/O space 0 = Makes serial channel 0 (COM1) accessible in both DOS I/O space 1 = Remaps serial channel 0 (COM1) address into expanded I/O space 0 = Makes the slave 82C59A interrupt controller accessible in both DOS...
Page 619: D.52 Rfsadd
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.52 RFSADD Refresh Address RFSADD (read/write) — — RA13 Number Mnemonic 15–14 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 13–1 RA13:1 Refresh Address Bits: These bits comprise A13:1 of the refresh address. —...
Page 620: D.54 Rfscir
D.54 RFSCIR Refresh Clock Interval RFSCIR (read/write) — — — Number Mnemonic 15–10 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. 9–0 RC9:0 Refresh Counter Value: Write the counter value to these ten bits. The interval counter counts down from this value.
Page 621: Scr N
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.56 SCR n Scratch Pad SCR0, SCR1 (read/write) Number Mnemonic 7–0 SP7:0 Writing and reading this register has no effect on SIO n operation. D-56 Expanded Addr: ISA Addr: Reset State: Function SCR0 SCR1 F4FFH F8FFH 03FFH...
Page 622: D.57 Siocfg
D.57 SIOCFG SIO and SSIO Configuration SIOCFG (read/write) — Number Mnemonic SIO1 Modem Signal Connections: 0 = Connects the SIO1 modem input signals to the package pins. 1 = Connects the SIO1 modem input signals internally. SIO0 Modem Signal Connections: 0 = Connects the SIO0 modem input signals to the package pins.
Page 623: D.58 Ssiobaud
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.58 SSIOBAUD SSIO Baud-rate Control SSIOBAUD (read/write) Number Mnemonic Baud-rate Generator Enable: Setting this bit enables the baud-rate generator. Clearing this bit disables the baud-rate generator, clears the baud-rate count value, and forces the baud rate clock to zero.
Page 624: D.59 Ssiocon1
D.59 SSIOCON1 SSIO Control 1 SSIOCON1 (read/write) THBE Number Mnemonic Transmit Underrun Error: The transmitter sets this bit to indicate a transmit underrun error in the TEN transfer mode. Clear this bit to clear the error flag. If a one is written to TUE, it is ignored and TUE retains its previous value.
Page 625: D.60 Ssiocon2
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.60 SSIOCON2 SSIO Control 2 SSIOCON2 (read/write) — — — Number Mnemonic 7–3 — Reserved. These bits are undefined; for compatibility with future devices, do not modify these bits. AUTOTXM Automatic Transmit off mode for master mode 0 = Clearing this bit puts the TEN bit into normal operation 1 = Setting this bit and the TXMM bit causes TEN to be ignored.
Page 626: D.62 Ssiorbuf
D.61 SSIOCTR Baud-rate Count Down SSIOCTR (read only) BSTAT Number Mnemonic BSTAT Baud-rate Generator Status: 0 = The baud-rate generator is disabled. 1 = The baud-rate generator is enabled. 6–0 CV6:0 Current Value: These bits indicate the current value of the baud-rate down counter. D.62 SSIORBUF Receive Holding Buffer SSIORBUF...
Page 627: D.63 Ssiotbuf
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.63 SSIOTBUF Transmit Holding Buffer SSIOTBUF (read/write) TB15 TB14 TB13 Number Mnemonic 15–0 TB15:0 Transmit Buffer Bits: These bits make up the next data word to be transmitted. The control logic loads this word into the transmit shift register. The transmit shift register shifts the bits out on the falling edge of the tranmitter clock pin.
Page 628: D.65 Tmrcfg
D.65 TMRCFG Timer Configuration TMRCFG (read/write) TMRDIS SWGTEN GT2CON Number Mnemonic TMRDIS Timer Disable: 0 = Enables the CLKIN n signals. 1 = Disables the CLKIN n signals. SWGTEN Software GATE n Enable 0 = Connects GATE n to either the V 1 = Enables GT2CON, GT1CON, and GT0CON to control the GT2CON Gate 2 Connection:...
Page 629: D.66 Tmrcon
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.66 TMRCON Timer Control (Control Word Format) TMRCON Number Mnemonic 7–6 SC1:0 Select Counter: Use these bits to specify a particular counter. The selections you make for bits 5–0 define this counter’s operation. 00 = counter 0 01 = counter 1 10 = counter 2 11 is not an option for TMRCON’s control word format.
Page 630: Tmr N
D.67 TMR n Timer n (Read Format) TMR n ( n = 0–2) Number Mnemonic 7–0 CV7:0 Count Value: These bits contain the counter’s count value. When reading the counter’s count value, follow the read selection specified in the counter’s control word.
Page 631 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Timer n (Status Format) TMR n ( n = 0–2) OUTPUT NULCNT Number Mnemonic OUTPUT Output Status: This bit indicates the current state of the counter’s output signal. 0 = OUT n is low 1 = OUT n is high NULCNT Count Status:...
Page 632: D.70 Ucsmskh
SYSTEM REGISTER QUICK REFERENCE D.68 UCSADH See “CSnADH (UCSADH)” on page D-8. D.69 UCSADL See “CSnADL (UCSADL)” on page D-9. D.70 UCSMSKH See “CSnMSKH (UCSMSKH)” on page D-10. D.71 UCSMSKL See “CSnMSKL (UCSMSKL)” on page D-11. D-67...
Page 633: Wdtcnth And Wdtcntl
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.72 WDTCNTH AND WDTCNTL WDT Counter Value (High) WDTCNTH (read only) WC31 WC30 WC29 WC23 WC22 WC21 WDT Counter Value (Low) WDTCNTL (read only) WC15 WC14 WC13 Bit Number Mnemonic High 15–0 WC31:16 WDT Counter Value High Word and Low Word: Read the high word of the counter value from WDTCNTH and the low Low 15–0 WC15:0...
Page 634: Wdtrldh And Wdtrldl
D.73 WDTRLDH AND WDTRLDL WDT Reload Value (High) WDTRLDH (read/write) WR31 WR30 WR29 WR23 WR22 WR21 WDT Reload Value (Low) WDTRLDL (read/write) WR15 WR14 WR13 Number Mnemonic High 15–0 WR31:16 WDT Reload Value (High Word and Low Word): Write the high word of the reload value to WDTRLDH and the low word Low 15–0 WR15:0 to the WDTRLDL.
Page 635: D.74 Wdtstatus
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL D.74 WDTSTATUS WDT Status WDTSTATUS (read/write) WDTEN — — Number Mnemonic WDTEN Watchdog Mode Enabled: This read-only bit indicates whether watchdog mode is enabled. Only a lockout sequence can set this bit and only a device reset can clear it. 0 = Watchdog mode disabled 1 = Watchdog mode enabled 6–2...
Page 636: Instruction Set Summary
INSTRUCTION SET SUMMARY...
Page 638: Instruction Encoding And Clock Count Summary
This appendix provides reference information for the Intel386™ processor family instruction set. The appendix is organized as follows: • Instruction Encoding and Clock Count Summary (see below) • Instruction Encoding (page E-22) INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY To calculate elapsed time for an instruction, multiply the instruction clock count, as listed in Table E-1, by the processor clock period (e.g., 62.5 ns for 16 MHz).
Page 639: E-1 Instruction Set Summary
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Wait states: Wait states add 1 clock per wait state to instruction execution for each data access. Table E-1 lists the instructions with their formats and execution times. The description of the notes for Table E-1 begins on page E-20. See “Instruction Encoding” on page E-22 for the defi- nition of the terms used in this table.
Page 640: Instruction Set Summary
Table E-1. Instruction Set Summary (Sheet 2 of 19) Instruction immediate 0 1 1 0 1 0 s 0 immediate data PUSHA = Push All 0 1 1 0 0 0 0 0 POP = Pop register/memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m register (short form) 0 1 0 1 1 reg...
Page 641 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 3 of 19) Instruction CLD = Clear direction 1 1 1 1 1 1 0 0 flag CLI = Clear interrupt 1 1 1 1 1 0 1 0 enable flag CLTS = Clear task 0 0 0 0 1 1 1 1...
Page 642 Table E-1. Instruction Set Summary (Sheet 4 of 19) Instruction SUB = Subtract register from register 0 0 1 0 1 0 d w mod reg r/m register from memory 0 0 1 0 1 0 0 w mod reg r/m memory from register 0 0 1 0 1 0 1 w mod reg r/m...
Page 643 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 5 of 19) Instruction MUL = multiply (unsigned) accumulator with 1 1 1 1 0 1 1 w mod 1 0 0 r/m register/memory multiplier — byte — word —...
Page 644 Table E-1. Instruction Set Summary (Sheet 6 of 19) Instruction IDIV = Integer divide (signed) Accumulator by 1 1 1 1 0 1 1 w mod 111 r/m register/memory divisor — byte — word — doubleword AAD = ASCII adjust for 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 divide...
Page 645 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 7 of 19) Instruction SHRD = Shift right double register/memory by 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 immediate register/memory by CL 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 1...
Page 646 Table E-1. Instruction Set Summary (Sheet 8 of 19) Instruction STRING MANIPULATION INSTRUCTIONS CMPS = Compare 1 0 1 0 0 1 1 w byte word INS = Input byte/word 0 1 1 0 1 1 0 w from DX port LODS = Load byte/word 1 0 1 0 1 1 0 w to AL/AX/EAX...
Page 647 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 9 of 19) Instruction register/memory, 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 register BTC = test bit and complement register/memory, 0 0 0 0 1 1 1 1 1 0 1 1 1 0 1 0...
Page 648 Table E-1. Instruction Set Summary (Sheet 10 of 19) Instruction Via call gate to different privilege level (no parameters) Via call gate to different privilege level (x parameters) From 286 task to 286 TSS From 286 task to Intel386 SX CPU TSS From 286 task to virtual 8086 task (Intel386 SX CPU TSS) From Intel386 SX CPU task to 286 TSS From Intel386 SX CPU task to Intel386 SX CPU TSS...
Page 649 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 11 of 19) Instruction within segment adding 1 1 0 0 0 0 1 0 16-bit displacement immed to SP intersegment 1 1 0 0 1 0 1 1 intersegment adding 1 1 0 0 1 0 1 0 16-bit displacement...
Page 650 Table E-1. Instruction Set Summary (Sheet 12 of 19) Instruction Full displacement 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 JBE/JNA = jump on below or equal/not above 8-bit displacement 0 1 1 1 0 1 1 0 8-bit displacement Full displacement 0 0 0 0 1 1 1 1...
Page 651 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 13 of 19) Instruction Full displacement 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 JLE/JNG = jump on less or equal/not greater 8-bit displacement 0 1 1 1 1 1 1 0 8-bit displacement...
Page 652 Table E-1. Instruction Set Summary (Sheet 14 of 19) Instruction SETBE/SETNA = set byte on below or equal/not above to register/memory 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 SETNBE/SETA = set byte on not below or equal/above to register/memory 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1...
Page 653 From 286 task to virtual 8086 mode via Task Gate From Intel386 SX CPU task to 286 TSS via Task Gate From Intel386 SX CPU task to Intel 386 SX CPU TSS via task gate From Intel386 SX CPU task to virtual 8086 mode via Task Gate...
Page 654 From 286 task to virtual 8086 mode via Task Gate From Intel386 SX CPU task to 286 TSS via Task Gate From Intel386 SX CPU task to Intel 386 SX CPU TSS via task gate From Intel386 SX CPU task to virtual 8086 mode via Task Gate...
Page 655 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 17 of 19) Instruction To different privilege level (within task) From 286 task to 286 TSS From 286 task to Intel386 SX CPU TSS From 286 task to virtual 8086 task From 286 task to virtual 8086 mode (within task) From Intel386 SX CPU task to 286 TSS From Intel386 SX CPU task to Intel386 SX CPU TSS...
Page 656 Table E-1. Instruction Set Summary (Sheet 18 of 19) Instruction PREFIX BYTES Address size prefix 0 1 1 0 0 1 1 1 LOCK = Bus lock prefix 1 1 1 1 0 0 0 0 Operand size prefix 0 1 1 0 0 1 1 0 Segment override prefix 0 0 1 0 1 1 1 0 0 0 1 1 1 1 1 0...
Page 657 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-1. Instruction Set Summary (Sheet 19 of 19) Instruction table register 0 0 0 0 1 1 1 1 SLDT = store local descriptor table to register/memory 0 0 0 0 1 1 1 1 SMSW = store machine 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1...
Page 658 b = 10 for register with immediate to register b = 11 for memory with immediate to register. An exception may occur, depending on the value of the operand. LOCK# is automatically asserted, regardless of the presence or absence of the LOCK# prefix. LOCK# is asserted during descriptor table accesses.
Page 659: E-1 General Instruction Format
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL INSTRUCTION ENCODING All instruction encodings are subsets of the general instruction format shown in Figure E-1. In- structions consist of one or two primary opcode bytes, possibly an address specifier consisting of the “mod r/m” byte and “scaled index” byte, a displacement if required, and an immediate data field if required.
Page 660: E-2 Fields Within Instructions
Table E-2. Fields Within Instructions Field Name Specifies if data is byte of full size (full size is either 16 or 32 bits) Specifies Direction of Data Operation Specifies if an Immediate Data Field must be Sign-Extended General Register Specifier mod r/m Address Mode Specifier (Effective Address can be a General Register) Scale Factor for Scaled Index Address Mode...
Page 661: Encoding Of Instruction Fields
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Unless specified otherwise, instructions with 8-bit and 16-bit operands do not affect the contents of the high-order bits of the extended registers. E.2.2 Encoding of Instruction Fields Within the instruction are several fields indicating register selection, addressing mode, and so on. The exact encodings of these fields are defined in the next several section.
Page 662: Encoding Of The Segment Register (Sreg) Field
Table E-5. Encoding of reg Field When w Field is Present in Instruction Register Specified by reg Field During 16-bit Data Operations Register Specified by reg Field During 32-bit Data Operations E.2.2.3 Encoding of the Segment Register (sreg) Field The sreg field in certain instructions is a 2-bit field allowing one of the four 80286 segment reg- isters to be specified.
Page 663: Encoding Of Address Mode
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL E.2.2.4 Encoding of Address Mode Except for special instructions, such as PUSH or POP, where the addressing mode is pre-deter- mined, the addressing mode for the current instruction is specified by addressing bytes following the primary opcode.
Page 664: E-7 Encoding Of 16-Bit Address Mode With "Mod R/M" Byte
Table E-7. Encoding of 16-bit Address Mode with “mod r/m” Byte mod r/m Effective Address 00 000 DS:[BX + SI] 00 001 DS:[BX + DI] 00 010 SS:[BP + SI] 00 011 SS:[BP + DI] 00 100 DS:[SI] 00 101 DS:[DI] 00 110 DS:d16...
Page 665: E-8 Encoding Of 32-Bit Address Mode With "Mod R/M" Byte (No S-I-B Byte Present)
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL Table E-8. Encoding of 32-bit Address Mode with “mod r/m” Byte (No s-i-b Byte Present) mod r/m Effective Address 00 000 DS:[EAX] 00 001 DS:[ECX] 00 010 SS:[EDX] 00 011 SS:[EBX] 00 100 s-i-b is present 00 101 DS:[d32] 00 110...
Page 666: E-9 Encoding Of 32-Bit Address Mode ("Mod R/M" Byte And S-I-B Byte Present)
Table E-9. Encoding of 32-bit Address Mode (“mod r/m” Byte and s-i-b Byte Present) mod r/m 00 000 00 001 00 010 00 011 00 100 00 101 00 110 00 111 01 000 01 001 01 010 01 011 01 100 01 101 01 110...
Page 667: Encoding Of Operation Direction (D) Field
Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL E.2.2.5 Encoding of Operation Direction (d) Field In many two-operand instructions the d field is present to indicate which operand is considered the source and which is the destination. Table E-10. Encoding of Operation Direction (d) Field “mod r/m”...
Page 668: Encoding Of Control Or Debug Or Test Register (Eee) Field
E.2.2.8 Encoding of Control or Debug or Test Register (eee) Field For the loading and storing of the Control, Debug and Test registers. Table E-13. When Interpreted as Control Register Field eee Code NOTE: Do not use any other encoding Table E-14.
Page 670: Glossary
GLOSSARY...
Page 672 This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1, GUIDE TO THIS MANUAL, discusses notational conventions.) Assert BIOS Boundary-scan Clear Deassert DOS Address Space The act of making a signal active (enabled). The polarity (high/low) is defined by the signal name.
Page 673 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL DOS-compatible Mode Edge-triggered Enhanced DOS Mode Expanded Address Space Idle Mode Interrupt Latency Glossary-2 be mapped into this space. In this manual, the terms DOS address and PC/AT address are synonymous. The addressing mode in which the internal timer, interrupt controller, serial I/O ports, and DMA controller are mapped into the DOS address space.
Page 674 Interrupt Response Time Interrupt Resolution JTAG Level-sensitive NonDOS Mode Nonintrusive DOS Mode Normally not-ready The amount of time required to complete an interrupt acknowledge cycle and transfer program control to the interrupt service routine. The delay between the time that the interrupt controller receives an interrupt request and the time that the master 82C59A presents the request to the CPU.
Page 675 Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL PC/AT Address Space Pipelining Powerdown Mode Reserved Bits SIO Unit SMRAM SSIO Unit Glossary-4 Addresses 0H–03FFH. The internal timers, interrupt controller, serial I/O ports, and DMA controller can be mapped into this space. In this manual, the terms DOS address and PC/AT address are synonymous.
Page 676 State Time (or State) Test-logic Unit UART communications. The transmitter and receiver can operate independently (with different clocks) to provide full-duplex communication. The basic time unit of the device; the combined period of the two internal timing signals, PH1 and PH2.
Page 678: Index
Index...
Page 680 #, defined, 82C59A, Address bus, Address lines new, Address space configuration register, expanded I/O, enabling/disabling, I/O decoding techniques, I/O for PC/AT systems, 4-15 peripheral registers, 4-14 Addressing modes, – 4-10 DOS-compatible mode, – 4-11 4-13 enhanced DOS mode, 4-11 4-14 nonDOS mode, 4-11 4-12...
Page 681 INTEL386™ EX MICROPROCESSOR USER’S MANUAL operation during idle mode, overview, – pipelining, 6-10 ready logic, See also Bus control arbitration signals, – Bus signals, departures from PC/AT architecture, – 14-11 Bus size control for chip-selects, 18-2 BYPASS, 15-1 CAS#-before-RAS# refresh, 14-1–14-24 Chip-select unit, 14-2...
Page 682 Deassert, defined, Decoding techniques, I/O address, Design considerations clock and power management unit, 16-10 input/output ports, 9-29 9-30 interrupt control unit, – 18-14 JTAG test-logic unit, 15-11 refresh control unit, 13-25 synchronous serial I/O unit, 5-37 Device configuration, – 5-28 procedure, 4-19 register addresses,...
Page 683 INTEL386™ EX MICROPROCESSOR USER’S MANUAL DOS compatibility departures from PC/AT architecture bus signals, CPU-only reset, DMA unit, HOLD, HLDA pins, interrupt control unit, SIO units, 15-12 DRAM, refreshing, DRAM, See Refresh control unit EISA compatibility, – ESE bit programming, Exceptions and interrupts, relative priority, Execution Unit, Expanded address, defined, Expanded I/O address space,...
Page 684 9-16 operation, – overview, 9-15 9-32 programming, – 9-32 considerations, 9-20 D-28 ICW1, 9-20 ICW1 register, 9-21 D-29 ICW2, 9-21 ICW2 register, 9-22 9-23 D-29 D-30 ICW3, 9-22 9-23 ICW3 register, 9-24 D-30 ICW4, 9-24 ICW4 register, IERn, 11-27, D-32 IIRn, 11-28, D-33 5-10 9-19...
Page 685 INTEL386™ EX MICROPROCESSOR USER’S MANUAL 4-15 register locations, Peripherals, summary, Physical address space, 5-23 Pin configuration, 5-24 10-23 11-17 12-31 PINCFG, 14-15 D-46 A-10 Pin descriptions, – Pin states after reset and during idle, powerdown, and hold, Pipelined instructions, defined, Port configuration 5-25 11-18...
Page 686 4-18 register addresses, 15-6 registers, 15-4 signals, Register naming conventions, 4-1–4-20 organization, Register bits, notational conventions, Register names, notational conventions, Register, status during SMM, Registers 18-2 BOUND, 18-2 BYPASS, 13-16 13-19 CLKPRS, 7-15 Component and revision ID, 14-14 14-17 CSnADH, 14-14 14-18 CSnADL,...
Page 687 INTEL386™ EX MICROPROCESSOR USER’S MANUAL 13-16 13-24 D-61 SSIOTBUF, TBRn, 11-15, 11-23, D-61 5-13 10-4 10-21 D-62 TMRCFG, 10-4 10-25 10-28 TMRCON, TMRn, 10-4, 10-26, 10-29, 10-32, D-64, D-65 14-14 14-17 UCSADH, 14-14 14-18 UCSADL, 14-14 14-19 D-10 UCSMSKH, 14-14 14-20 D-11 UCSMSKL,...
Page 688 13-5 13-15 operation, – 13-5 13-6 baud-rate generator, – 13-12 13-15 receiver, – 13-6 transmitter, 13-1 13-4 overview, – 13-16 13-25 programming, – 13-19 CLKPRS register, 13-17 PINCFG, 13-18 SIOCFG register, 13-20 D-58 SSIOBAUD, 13-20 SSIOBAUD register, 13-22 D-59 SSIOCON1, 13-21 SSIOCON1 register, 13-23...
Page 689 INTEL386™ EX MICROPROCESSOR USER’S MANUAL 10-12 10-15 mode 3, – 10-13 10-14 basic operation, – basic operation (odd count), 10-14 disabling the count, 10-15 writing a new count, 10-16 10-17 mode 4, – 10-16 basic operation, 10-17 disabling the count, 10-17 writing a new count, 10-18...
Page 690 17-7 registers, 17-7 WDTCLR, 17-7 WDTCNTH, 17-7 WDTCNTL, 17-7 WDTRLDH, 17-7 WDTRLDL, 17-7 WDTSTATUS, 17-4 reload event, 17-3 signals, WDT, See Watchdog timer unit Worksheets 5-34 peripheral configuration, 5-34 pin configuration, World Wide Web, INDEX Index-11...

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