Intel ® 80331 I/O Processor Ddr Overview; Core Speed And Memory Configuration - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
®
7.2 Intel
80331 with the DDR-SDRAM memory sub-system needs continuous ground referencing for all
DDR signals. The DDR channel requires the referencing stack-up to allow ground referencing on
all of the DDR signals from the 80331 to the parallel termination at the end of the channel.
Note: Leave unused M_CKs and M_CK#s unconnected.
The 80331 signal integrity specifications are for a single DIMM only for both DDR333 and DDR
II 400. The DIMM topology supported for the recommendations listed in this section are for x8
single / double banks and x16 single/double banks.
DDR333 = single DIMM and supports both Buffered / Unbuffered DIMM
DDRII 400 = single DIMM and supports Buffered DIMM
Table 29
Table 29.

Core Speed and Memory Configuration

The DDR interface is divided up into three groups that each have special routing guidelines:
•
Source synchronous signal group: DQ/DQS/DQM/CB signals
•
Clocked: M_CK signals
•
Control signals: Address/RAS/CAS/CS/WE/CKE signals
68
80331 I/O Processor DDR Overview
details the 80331 Core Speed and DDR/DDRII memory configuration.
Core/DDR
Low
Medium
High
DDR333
500MHz
667MHz
N/A
DDR-II 400
500MHz
N/A
800MHz