Intel BX80623I32100 Datasheet
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Intel BX80623I32100 Datasheet

Core i7, i5, and i3 desktop processor series, pentium processor g800 and g600 series, celeron processor g500 and g400 series
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2nd Generation Intel
Processor Family Desktop, Intel
Pentium
and Intel
Family Desktop
Datasheet, Volume 1
Supporting Intel
Supporting Intel
Supporting Intel
This is Volume 1 of 2
June 2013
®
Processor Family Desktop,
®
Celeron
®
Core™ i7, i5, and i3 Desktop Processor Series
®
®
Pentium
Processor G800 and G600 Series
®
®
Celeron
Processor G500 and G400 Series
®
Core™
®
Processor
Document Number: 324641-008
®

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Summary of Contents for Intel BX80623I32100

  • Page 1 ® 2nd Generation Intel Core™ ® Processor Family Desktop, Intel ® Pentium Processor Family Desktop, ® ® and Intel Celeron Processor Family Desktop Datasheet, Volume 1 ® Supporting Intel Core™ i7, i5, and i3 Desktop Processor Series ® ® Supporting Intel...
  • Page 2 Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses.

  • Page 3: Table Of Contents

    1.2.4 Platform Environment Control Interface (PECI) ........... 14 1.2.5 Processor Graphics ................. 14 ® ® 1.2.6 Intel Flexible Display Interface (Intel FDI) ..........14 Power Management Support ................15 1.3.1 Processor Core..................15 1.3.2 System ....................15 1.3.3 Memory Controller.................. 15 1.3.4...
  • Page 4 ® ® Intel Advanced Vector Extensions (Intel AVX)............40 ® ® Intel Advanced Encryption Standard New Instructions (Intel AES-NI) ....40 3.6.1 PCLMULQDQ Instruction ................40 ® Intel 64 Architecture x2APIC ................40 Power Management ....................43 Advanced Configuration and Power Interface (ACPI) States Supported ......44 4.1.1...
  • Page 5 PCI Express* Power Management ................ 55 Direct Media Interface (DMI) Power Management ..........55 Graphics Power Management ................56 ® ® 4.6.1 Intel Rapid Memory Power Management (Intel RMPM) (also known as CxSR) ................56 ® ® 4.6.2 Intel Graphics Performance Modulation Technology (Intel GPMT) ....
  • Page 6 Reset and Miscellaneous Signals................64 PCI Express* Graphics Interface Signals..............65 ® ® Intel Flexible Display Interface (Intel FDI) ..............65 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface ......66 Phase Lock Loop (PLL) Signals ..................66 6-10 Test Access Points (TAP) Signals ................66...
  • Page 7 6-11 Error and Thermal Protection Signals ................. 67 6-12 Power Sequencing Signals..................67 6-13 Processor Power Signals ..................68 6-14 Sense Signals......................68 6-15 Ground and Non-Critical to Function (NCTF) Signals ............ 68 6-16 Processor Internal Pull-Up / Pull-Down Resistors ............69 VR 12.0 Voltage Identification Definition ..............

  • Page 8: Revision History

    • Added Intel Core™ i5-2405S, i5-2310, and i3-2105 processors ® ® ® • Added Intel Pentium processor family desktop – Intel May 2011 ® Pentium G850, G840, G620, and G620T processors ® • Added Intel Core™ i5-2320, i3-2125, i3-2130, and i3-2120T...

  • Page 9: Introduction

    ® Note: Throughout this document, 2nd Generation Intel Core™ processor family desktop, ® ® ®...

  • Page 10: Desktop Platform System Block Diagram Example

    Digital Display x 3 Management Engine USB 2.0 Platform LVDS Flat Panel Controller Hub (PCH) Intel® HD Audio Analog CRT SPI Flash x 2 SMBUS 2.0 Controller Link 1 PCI Express* WiFi / WiMax 8 PCI Express* 2.0 x1 Ports...

  • Page 11: Processor Feature Details

    • Intel Advanced Vector Extensions (Intel AVX) ® ® • Intel Advanced Encryption Standard New Instructions (Intel AES-NI) • PCLMULQDQ Instruction Interfaces 1.2.1 System Memory Support • Two channels of unbuffered DDR3 memory with a maximum of two UDIMMs or SO- DIMMs (for AIO) per channel •...

  • Page 12: Pci Express

    • Command launch modes of 1n/2n • On-Die Termination (ODT) • Asynchronous ODT ® ® • Intel Fast Memory Access (Intel FMA) — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling 1.2.2 PCI Express* • PCI Express* port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0.

  • Page 13: Direct Media Interface (Dmi)

    Introduction • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response.

  • Page 14: Platform Environment Control Interface (Peci)

    • The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption. • Next Generation Intel Clear Video Technology HD support is a collection of video playback and enhancement features that improve the end user’s viewing experience.

  • Page 15: Power Management Support

    ® ® • Intel Graphics Performance Modulation Technology (Intel GPMT) • Intel Smart 2D Display Technology (Intel S2DDT) • Graphics Render C-State (RC6) Thermal Management Support • Digital Thermal Sensor • Intel Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support •...

  • Page 16: Package

    (Virtual Machine Manager or OS) ® Intel VT-d control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. I/O Virtualization...
  • Page 17 Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. ® Processor Graphics Intel Processor Graphics A unit of DRAM corresponding four to eight devices in parallel. These devices are Rank usually, but not always, mounted on a single side of a SO-DIMM.

  • Page 18: Related Documents

    Table 1-3 for additional information. Table 1-3. Related Documents Document Document Number/ Location ® ® ® 2nd Generation Intel Core™ Processor Family Desktop, Intel Pentium http://download.intel.com/design ® ® Processor Family Desktop, and Intel Celeron Processor Family Desktop /processor/datashts/324642.pdf Datasheet, Volume 2 ®...

  • Page 19: Interfaces

    Interfaces Interfaces This chapter describes the interfaces supported by the processor. System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependant on the PCH SKU in the target platform.

  • Page 20: Supported Udimm Module Configurations

    Interfaces Table 2-1. Supported UDIMM Module Configurations # of # of # of # of DIMM DRAM Device DRAM Physical Row/Col Banks Card DRAM Page Size Capacity Technology Organization Device Address Inside Version Devices Ranks Bits DRAM Unbuffered/Non-ECC Supported DIMM Module Configurations 1 GB 1 Gb 128 M X 8...

  • Page 21: System Memory Timing Support

    Dual-Channel Mode – Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a symmetric and an asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached.

  • Page 22: Rules For Populating Memory Slots

    Interfaces ® Figure 2-1. Intel Flex Memory Technology Operation T O M N o n in t e r le a v e d a c c e s s D u a l c h a n n e l...

  • Page 23: Fma)

    ® (Intel FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.

  • Page 24: Pci Express* Interface

    Interfaces PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1 for details.

  • Page 25: Transaction Layer

    Interfaces handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

  • Page 26: Pci Express* Configuration Mechanism

    Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4. PCI Express* Related Register Structures in the Processor PCI-PCI Bridge representing PCI Compatible PEG0 root PCI Host Bridge Express* Express* ports Device Device...

  • Page 27: Pci Express* Lanes Connection

    DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0. 2.3.2 Processor / PCH Compatibility Assumptions ® Intel 6 Series Chipset The processor is compatible with the PCH. The processor is not compatible with any previous PCH products.

  • Page 28: Dmi Link Down

    Interfaces 2.3.3 DMI Link Down The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH.

  • Page 29: And Video Engines For Graphics Processing

    Interfaces 2.4.1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the following performance and power-management enhancements: •...

  • Page 30: Video Engine

    Interfaces 2.4.1.2.6 Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels.

  • Page 31: Processor Graphics Display

    Interfaces 2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes • DisplayPort and Intel FDI Figure 2-7. Processor Display Block Diagram Display Display Port Pipe A...

  • Page 32: Intel ® Flexible Display Interface

    FDI) is a proprietary link for carrying display ® traffic from the Processor Graphics controller to the PCH display I/Os. Intel supports two independent channels—one for pipe A and one for pipe B. • Each channel has four transmit (Tx) differential pairs used for transporting pixel and framing data from the display engine.

  • Page 33: Platform Environment Control Interface (Peci)

    Interfaces Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (processor) and a PECI master. The processor implements a PECI interface • Allow communication of processor thermal and other information to the PECI master.
  • Page 34 Interfaces Datasheet, Volume 1...

  • Page 35: Technologies

    OSs and applications without any special steps. • Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.

  • Page 36: Vt-X) Features

    I/O (Intel VT-d) Objectives The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system.

  • Page 37: Intel I/O (Intel Virtualization Technology (Intel Vt-D) Features

    The following features are not supported by the processor with Intel VT-d: • No support for PCISIG endpoint caching (ATS) • No support for Intel VT-d read prefetching/snarfing (that is, translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations).

  • Page 38: Intel Trusted Execution Technology (Intel Txt)

    Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.

  • Page 39: Intel Turbo Boost Technology

    Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency/render clock if it is operating below power, temperature, and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads.

  • Page 40: Intel Advanced Vector Extensions (Intel Avx)

    Advanced Vector Extensions (Intel AVX) Intel Advanced Vector Extensions (Intel AVX) is the latest expansion of the Intel instruction set. It extends the Intel Streaming SIMD Extensions (Intel SSE) from 128- bit vectors into 256-bit vectors. Intel AVX addresses the continued need for vector...
  • Page 41 The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations. Note: Intel x2APIC technology may not be available on all processor SKUs. ® For more information, refer to the Intel 64 Architecture x2APIC Specification at http://www.intel.com/products/processor/manuals/...
  • Page 42 Technologies Datasheet, Volume 1...

  • Page 43: Power Management

    Power Management Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller Figure 4-1.

  • Page 44: Advanced Configuration And Power Interface (Acpi) States Supported

    Power Management Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State Description G0/S0 Full On G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD).

  • Page 45: Direct Media Interface (Dmi) States

    Power Management 4.1.5 Direct Media Interface (DMI) States Table 4-5. Direct Media Interface (DMI) States State Description Full on – Active transfer state First Active Power Management low power state – Low exit latency Lowest Active Power Management – Longer exit latency Lowest power state (power-off) –...

  • Page 46: Processor Core Power Management

    Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.

  • Page 47: Idle Power Management Breakdown Of The Processor Cores

    Power Management Figure 4-2. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.

  • Page 48: Requesting Low-Power Idle States

    Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.

  • Page 49: Core C1/C1E State

    MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal ® state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.

  • Page 50: Package C-States

    Power Management 4.2.5 Package C-States The processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package C- states unless specified otherwise: • A package C-state request is determined by the lowest numerical core C-state amongst all cores.

  • Page 51: Package C0

    Power Management Figure 4-4. Package C-State Entry and Exit 4.2.5.1 Package C0 This is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state.

  • Page 52: Package C3 State

    Power Management 4.2.5.3 Package C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state. • The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform.

  • Page 53: Dram Power Management And Initialization

    Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals that the SDRAM controller supports. The processor drives four CKE pins to perform these operations.

  • Page 54: Initialization Role Of Cke

    Conditional Self-Refresh Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into self-refresh in the package C3 and C6 low-power states. Intel RMPM functionality depends on the graphics/display state (relevant only when processor graphics is being used), as well as memory traffic patterns generated by other connected I/O devices.

  • Page 55: Dynamic Power-Down Operation

    Power Management 4.3.2.3 Dynamic Power-down Operation Dynamic power-down of memory is employed during normal operation. Based on idle conditions, a given memory rank may be powered down. The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power-down state. The processor core controller can be configured to put the devices in active power- down (CKE de-assertion with open pages) or precharge power-down (CKE de-assertion with all pages closed).

  • Page 56: Graphics Power Management

    C3/C6 to allow the system to remain in the lower power states longer. Desktop processors routinely save power during runtime conditions by entering the C3, C6 state. Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole.

  • Page 57: Thermal Power Management

    The graphics driver dynamically adjusts between P-States to maintain optimal performance, power, and thermals. The graphics driver will always place the graphics engine in its lowest possible P-State; thereby, acting in the same capacity as Intel GPMT. Thermal Power Management Section 4.6 for all graphics thermal power management-related features.
  • Page 58 Power Management Datasheet, Volume 1...

  • Page 59: Thermal Management

    Thermal Management Thermal Management ® For thermal specifications and design guidelines, refer to the 2nd Generation Intel ® ® Core™ Processor Family Desktop, Intel Pentium Processor Family Desktop, and ® ® Intel Celeron Processor Family Desktop, and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines.
  • Page 60 Thermal Management Datasheet, Volume 1...

  • Page 61: Signal Description

    Signal Description Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type Input Pin Output Pin Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal (see Table...

  • Page 62: System Memory Interface Signals

    Signal Description System Memory Interface Signals Table 6-2. Memory Channel A Signals Direction/ Signal Name Description Buffer Type Bank Select: These signals define which banks are selected within SA_BS[2:0] each SDRAM rank. DDR3 Write Enable Control Signal: This signal is used with SA_RAS# and SA_WE# SA_CAS# (along with SA_CS#) to define the SDRAM Commands.

  • Page 63: Memory Reference And Compensation Signals

    Signal Description Table 6-3. Memory Channel B Signals Direction/ Signal Name Description Buffer Type Bank Select: These signals define which banks are selected within SB_BS[2:0] each SDRAM rank. DDR3 Write Enable Control Signal: This signal is used with SB_RAS# and SB_WE# SB_CAS# (along with SB_CS#) to define the SDRAM Commands.

  • Page 64: Reset And Miscellaneous Signals

    Signal Description Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals Direction/ Signal Name Description Buffer Type Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for this lane.

  • Page 65: Pci Express*-Based Interface Signals

    PCI Express Transmit Differential Pair PEG_TX#[15:0] PE_TX[3:0] PCI Express PE_TX#[3:0] Notes: PE_TX[3:0] and PE_RX[3:0] are only used for platforms that support 20 PCIe lanes. ® ® Intel Flexible Display Interface (Intel FDI) Signals ® ® Table 6-7. Intel Flexible Display Interface (Intel FDI) Direction/...

  • Page 66: Direct Media Interface (Dmi) Signals

    Signal Description Direct Media Interface (DMI) Signals Table 6-8. Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface Direction/ Signal Name Description Buffer Type DMI_RX[3:0] DMI Input from PCH: Direct Media Interface receive differential pair. DMI_RX#[3:0] DMI_TX[3:0] DMI Output to PCH: Direct Media Interface transmit differential pair. DMI_TX#[3:0] Phase Lock Loop (PLL) Signals Table 6-9.

  • Page 67: Error And Thermal Protection Signals

    Signal Description Error and Thermal Protection Signals Table 6-11. Error and Thermal Protection Signals Direction/ Signal Name Description Buffer Type Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.

  • Page 68: Processor Power Signals

    Signal Description 6.11 Processor Power Signals Table 6-13. Processor Power Signals Direction/ Signal Name Description Buffer Type Processor core power rail VCCIO Processor power for I/O VDDQ Processor I/O supply voltage for DDR3 VCCAXG Graphics core power supply. VCCPLL VCCPLL provides isolated power for internal processor PLLs VCCSA System Agent power supply VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial...

  • Page 69: Processor Internal Pull-Up / Pull-Down Resistors

    Signal Description 6.14 Processor Internal Pull-Up / Pull-Down Resistors Table 6-16. Processor Internal Pull-Up / Pull-Down Resistors Signal Name Pull-Up / Pull-Down Rail Value BPM[7:0] Pull Up VCCIO 65–165 Ω PRDY# Pull Up VCCIO 65–165 Ω PREQ# Pull Up VCCIO 65–165 Ω...
  • Page 70 Signal Description Datasheet, Volume 1...

  • Page 71: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Lands The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane.

  • Page 72: Processor Clocking (Bclk[0], Bclk#[0])

    Electrical Specifications Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core operating frequency, memory controller frequency, system agent frequencies, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency.

  • Page 73: Vr 12.0 Voltage Identification Definition

    Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3) CC_MAX CC_MAX 0.00000 0.88500 0.25000 0.89000 0.25500 0.89500 0.26000 0.90000 0.26500 0.90500 0.27000 0.91000 0.27500 0.91500 0.28000 0.92000 0.28500 0.92500 0.29000 0.93000 0.29500 0.93500 0.30000 0.94000 0.30500 0.94500 0.31000 0.95000...
  • Page 74 Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 2 of 3) CC_MAX CC_MAX 0.46000 1.10000 0.46500 1.10500 0.47000 1.11000 0.47500 1.11500 0.48000 1.12000 0.48500 1.12500 0.49000 1.13000 0.49500 1.13500 0.50000 1.14000 0.50500 1.14500 0.51000 1.15000 0.51500 1.15500 0.52000 1.16000 0.52500 1.16500...
  • Page 75 Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 3 of 3) CC_MAX CC_MAX 0.67500 1.31500 0.68000 1.32000 0.68500 1.32500 0.69000 1.33000 0.69500 1.33500 0.70000 1.34000 0.70500 1.34500 0.71000 1.35000 0.71500 1.35500 0.72000 1.36000 0.72500 1.36500 0.73000 1.37000 0.73500 1.37500 0.74000 1.38000...

  • Page 76: System Agent (Sa) Vcc Vid

    Future Intel processors Note 1 Notes: Some of V configurations are reserved for future Intel processor families. CCSA Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – These signals should not be connected.

  • Page 77: Signal Groups

    Electrical Specifications Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On- Die Termination (ODT) resistors.

  • Page 78: Test Access Port (Tap) Connection

    Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.

  • Page 79: Storage Conditions Specifications

    JESD22-A103 (high temp) standards when applicable for volatile memory. Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits...

  • Page 80: Dc Specifications

    Electrical Specifications 7.10 DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-5, Table...
  • Page 81 VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ...

  • Page 82: Processor System Agent I/O Buffer Supply Dc Voltage And Current Specifications

    Electrical Specifications Table 7-6. Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Unit Note Voltage for the system agent 0.879 0.925 0.971 CCSA Processor I/O supply voltage for 1.425 1.575 DDR3 PLL supply voltage (DC + AC 1.71 1.89 CCPLL...

  • Page 83: Supply Dc Voltage And Current Specifications

    VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). Datasheet, Volume 1...

  • Page 84: Ddr3 Signal Group Dc Specifications

    Electrical Specifications Table 7-8. DDR3 Signal Group DC Specifications Symbol Parameter Units Notes Input Low Voltage — — SM_VREF – 0.1 Input High Voltage SM_VREF + 0.1 — — Output Low Voltage / 2)* (R — — TERM Output High Voltage –...

  • Page 85: Control Sideband And Tap Signal Group Dc Specifications

    Electrical Specifications Table 7-9. Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Units Notes Input Low Voltage — * 0.3 CCIO Input High Voltage * 0.7 — 2, 4 CCIO Output Low Voltage — * 0.1 CCIO Output High Voltage * 0.9 —...

  • Page 86: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 87: Dc Characteristics

    Electrical Specifications 7.11.2 DC Characteristics The PECI interface operates at a nominal voltage set by V . The set of DC electrical CCIO specifications shown in Table 7-11 is used with devices normally operating from a V CCIO interface supply. V nominal levels will vary between processor families.
  • Page 88 Electrical Specifications Datasheet, Volume 1...

  • Page 89: Processor Pin And Signal Information

    Processor Pin and Signal Information Processor Pin and Signal Information Processor Pin Assignments The processor pinmap quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-1 provides a listing of all processor pins ordered alphabetically by pin name. Datasheet, Volume 1...

  • Page 90: Socket Pinmap (Top View, Upper-Left Quadrant)

    Processor Pin and Signal Information Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDDQ VDDQ VDDQ VSS_NCTF SA_BS[0] SA_MA[1] SA_ DQ[3 7 ] SA_ CK#[2 ] SA_ CK[0 ] NCTF...

  • Page 91: Socket Pinmap (Top View, Upper-Right Quadrant)

    Processor Pin and Signal Information Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant) 20 19 18 17 16 15 14 13 12 11 10 RSVD RSVD RSVD SB_CKE[1] SB_ MA[9 ] SB_ MA[1 4 ] SA_ DQ[3 1 ] SA_ DQ[2 4 ] SA_ DQ[2 3 ] RSVD_ NCTF VSS VSS...

  • Page 92: Socket Pinmap (Top View, Lower-Left Quadrant)

    Processor Pin and Signal Information Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant) VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VSS VSS VSS VSS VSS VSS VSS VSS VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG RSVD RSVD...

  • Page 93: Socket Pinmap (Top View, Lower-Right Quadrant)

    Processor Pin and Signal Information Figure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant) DMI_RX[2] DMI_ TX#[2 ] DMI_ TX[2 ] DM I_RX#[2] VCCIO DMI_RX[0] BCLK[0] BCLK#[0] DMI_ TX#[1 ] DMI_ TX[1 ] DM I_RX#[0] VSS VSS VCCIO DMI_RX[1] DMI_ TX[0 ] DMI_ TX#[0 ] DM I_RX#[1] VCCIO VCCIO VCCIO...

  • Page 94: Processor Pin List By Pin Name

    Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. BCLK_ITP Diff Clk DMI_TX#[0] BCLK_ITP# Diff Clk DMI_TX#[1] BCLK[0]...
  • Page 95 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. PE_TX[2] PCI Express PEG_TX[2] PCI Express PE_TX[3] PCI Express PEG_TX[3]...
  • Page 96 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. RSVD AJ30 SA_BS[2] AV20 DDR3 RSVD AJ31 SA_CAS#...
  • Page 97 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SA_DQ[26] DDR3 SA_DQS[6] AK38 DDR3 SA_DQ[27] DDR3 SA_DQS[7]...
  • Page 98 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SB_BS[2] AW17 DDR3 SB_DQ[26] AR13 DDR3 SB_CAS# AK25...
  • Page 99 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SB_DQS[6] AL33 DDR3 SM_DRAMRST# AW18 DDR3 SB_DQS[7] AG35...
  • Page 100 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. Datasheet, Volume 1...
  • Page 101 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VCCAXG AB38 VCCAXG AB39 VCCAXG AB40 VCCAXG AC33...
  • Page 102 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VCCIO VCCPLL AK12 VCCIO AG33 VCCSA VCCIO AJ16...
  • Page 103 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AJ25 AA33 AJ27 AA34 AJ36 AA35 AA36 AA37...
  • Page 104 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AM30 AR18 AM36 AR19 AM37 AR27 AM38 AR30...
  • Page 105 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AV11 AV14 AV17 AV35 AV38 AW10 AW11 AW14...
  • Page 106 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Table 8-1. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. Datasheet, Volume 1...
  • Page 107 Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VSS_NCTF VSS_NCTF AV39 VSS_NCTF AY37 VSS_NCTF VSS_SENSE Analog VSSAXG_SENSE Analog VSSIO_SENSE Analog § § Datasheet, Volume 1...
  • Page 108 Processor Pin and Signal Information Datasheet, Volume 1...

  • Page 109: Ddr Data Swizzling

    DDR Data Swizzling DDR Data Swizzling To achieve better memory performance and better memory timing, Intel design performed the DDR Data pin swizzling that will allow a better use of the product across different platforms. Swizzling has no effect on functional operation and is invisible to the OS/SW.

  • Page 110: Ddr Data Swizzling Table - Channel A

    DDR Data Swizzling Table 9-1. DDR Data Swizzling Table 9-1. DDR Data Swizzling Table – Channel A Table – Channel A Pin Name Pin # MC Pin Name Pin Name Pin # MC Pin Name SA_DQ[0] DQ01 SA_DQ[41] AR37 DQ42 SA_DQ[1] DQ02 SA_DQ[42]...

  • Page 111: Ddr Data Swizzling Table - Channel B

    DDR Data Swizzling Table 9-2. DDR Data Swizzling Table 9-2. DDR Data Swizzling Table – Channel B Table – Channel B Pin Name Pin # MC Pin Name Pin Name Pin # MC Pin Name SB_DQ[0] DQ03 SB_DQ[41] AP31 DQ43 SB_DQ[1] DQ02 SB_DQ[42]...
  • Page 112 DDR Data Swizzling Datasheet, Volume 1...

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