Intel NetStructure ZT 5504 Manuals

Manuals and User Guides for Intel NetStructure ZT 5504. We have 1 Intel NetStructure ZT 5504 manual available for free PDF download: Manual

Intel NetStructure ZT 5504 Manual

Intel NetStructure ZT 5504 Manual (84 pages)

System Master Processor Board

Brand: Intel | Category: Computer Hardware | Size: 0.48 MB

Table of Contents

- 4
  Table of Contents
- 9
  Tables
- 10
  Figures
- 11
  Manual Organization
12
1 Introduction
- 12
  Product Definition
- 13
  Features
- 13
  ZT 5504 Faceplate
- 15
  Functional Blocks
  - 15
    Compactpci/Psb Architecture
  - 15
    Functional Block Diagram
  - 16
    Processor
  - 16
    Chipset
  - 16
    PCI-To-PCI Bridge (P2P)
  - 17
    Memory and I/O Addressing
  - 17
    Drone Mode
  - 17
    Power Ramp Circuitry
  - 18
    Rear-Panel I/O
  - 18
    PCI Video
  - 18
    Fault Current Limits
  - 19
    PCI Mezzanine Card (PMC) Interface
  - 19
    Dual Ethernet Interfaces
  - 19
    IDE Hard Drive
  - 19
    Serial I/O
  - 20
    Interrupts
  - 20
    Counter/Timers
  - 21
    Dma
  - 21
    Real-Time Clock
  - 21
    Reset
  - 21
    Two-Stage Watchdog Timer
  - 21
    Universal Serial Bus (USB)
  - 22
    Baseboard Management Controller
  - 22
    IDE Controller
  - 22
    Floppy Disk Controller
  - 22
    Keyboard and Mouse Controller
  - 22
    LED Indicators
- 23
  Software
24
2 Getting Started
- 24
  Unpacking
- 24
  System Requirements
  - 24
    BIOS Version
  - 24
    Connectivity
  - 25
    Electrical and Environmental
- 26
  Memory Configuration
- 27
  Memory Address Map Example
- 28
  I/O Address Map
- 29
  I/O Configuration
- 29
  Connectors
- 29
  Switches and Cuttable Traces
- 29
  BIOS Configuration Overview
- 29
  Setup Screen
- 30
  Operating System Installation
32
3 Configuration
40
4 Reset
- 40
  Reset Types and Sources
  - 40
    Hard Reset Sources
  - 40
    Soft Reset Sources
  - 41
    Backend Power down Sources
  - 41
    NMI Sources
42
5 System Monitoring and Control
- 42
  Monitoring and Control Functions
- 43
  Smbus Address Map
45
6 IDE Controller
- 45
  Features of the IDE Controller
- 45
  Disk Drive Support
  - 45
    Primary IDE Channel
  - 45
    Secondary IDE Channel
- 46
  I/O Mapping
- 46
  Compactflash Carrier
- 46
  Device Drivers
47
7 Watchdog Timer
- 47
  Watchdog Timer Overview
  - 47
    Watchdog Timer Architecture
  - 48
    Power up Initialization
  - 48
    Timeout Values
- 48
  Using the Watchdog in an Application
  - 48
    Watchdog Reset
  - 49
    Watchdog NMI
    - 50
      Chaining the Isrs
    - 50
      Enabling the Watchdog NMI
    - 51
      NMI Handler
52
8 BIOS Recovery
- 52
  Flash
- 52
  BIOS Recovery Socket Location
- 53
  BIOS Recovery Module
  - 53
    Flash Utility Program
- 54
  Specifications
- 68
  Thermal Considerations
  - 68
    Thermal Requirements
  - 69
    Temperature Monitoring
- 70
  System Registers
  - 70
    System Register Definitions
    - 71
      Flash Control (78H)
    - 72
      Watchdog (79H)
    - 75
      J1 IPMB Control (7Bh)
    - 75
      Port 80 BIOS POST Codes (80H)
    - 76
      Event Monitors (E1H)
    - 76
      Switch Monitors (E3H)
    - 77
      Geographic Addressing (E4H)
    - 78
      Control Bits (E5H)
    - 78
      J5 Smbus Enable (E6H)
- 79
  Datasheet Reference
  - 79
    Board Serial Number
  - 79
    Compactpci
  - 79
    Ethernet
  - 79
    Intel 440GX Agpset
  - 80
    Mobile Pentium III Processor - M in BGA2 Package
  - 80
    PCI-To-PCI Bridge
  - 80
    PMC Specification
  - 80
    Superi/O
  - 80
    Video
- 81
  Agency Approvals

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