Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual
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Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Dual-core intel itanium processor 9000 and 9100 series
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Dual-Core Intel
9000 and 9100 Series
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
®
Intel
Itanium
Processor 1.6 GHz with 6 MB L3 Cache 9010
Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
Dual-Core Intel
Itanium
®
®
Intel
Itanium
Processor 1.6 GHz with 12 MB L3 Cache 9110N
Datasheet
October 2007
®
Itanium
®
Processor 1.6 GHz with 24 MB L3 Cache 9050
®
Processor 1.6 GHz with 18 MB L3 Cache 9040
®
Processor 1.6 GHz with 8 MB L3 Cache 9030
®
Processor 1.42 GHz with 12 MB L3 Cache 9020
®
Processor 1.4 GHz with 12 MB L3 Cache 9015
®
Processor 1.66 GHz with 24 MB L3 Cache 9150M
®
Processor 1.6 GHz with 24 MB L3 Cache 9150N
®
Processor 1.66 GHz with 18 MB L3 Cache 9140M
®
Processor 1.6 GHz with 18 MB L3 Cache 9140N
®
Processor 1.42 GHz with 12 MB L3 Cache 9120N
®
Processor 1.66 GHz with 8 MB L3 Cache 9130M
®
Processor
Document Number: 314054-002

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Summary of Contents for Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor

  • Page 1 Processor 1.4 GHz with 12 MB L3 Cache 9015 ® ® Intel Itanium Processor 1.6 GHz with 6 MB L3 Cache 9010 Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152 ® ® Dual-Core Intel Itanium Processor 1.66 GHz with 24 MB L3 Cache 9150M ®...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-4725, or by visiting Intel's website at http://www.intel.com.

  • Page 3: Table Of Contents

    Terminology ..................... 12 State of Data ....................12 Reference Documents ..................13 Electrical Specifications ....................15 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series System Bus ....15 2.1.1 System Bus Power Pins ................ 15 2.1.2 System Bus No Connect ............... 15 System Bus Signals ...................
  • Page 4 A.1.38 IDS# (I)....................99 A.1.39 IGNNE# (I)....................99 A.1.40 INIT# (I) ....................99 A.1.41 INT (I) ....................100 A.1.42 IP[1:0]# (I) ..................100 A.1.43 LEN[2:0]# (I/O) ................... 100 A.1.44 LINT[1:0] (I) ..................100 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 5 System Bus Reset and Configuration Timings for Cold Reset........31 System Bus Reset and Configuration Timings for Warm Reset ......... 32 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Pinout......35 Processor Package..................... 66 Package Height and Pin Dimensions ..............67 Processor Package Mechanical Interface Dimensions ..........
  • Page 6 Processor Package Mechanical Interface Dimensions ..........68 Processor Package Load Limits at Power Tab ............71 Case Temperature Specification ................77 System Management Interface Signal Descriptions ..........79 ® Thermal Sensing Device SMBus Addressing on the Dual-Core Intel ® Itanium Processor 9000 and 9100 series.............81 ®...
  • Page 7 A-11 STBp[7:0]# and STBn[7:0]# Associations ............104 A-12 Output Signals ....................105 A-13 Input Signals ....................105 A-14 Input/Output Signals (Single Driver) ..............106 A-15 Input/Output Signals (Multiple Driver)..............107 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 8: Revision History

    • Updated with 9100 series product information; updated brand name from 314054 -002 October 2007 “Itanium 2” to “Itanium”. 314054 -001 • Initial release of the document. July 2006 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 9: Product Features

    — Minimize L3 cache errors. and speculation, resulting in superior Outstanding Energy Efficiency. Instruction-Level Parallelism (ILP). — 20 percent less power than previous Intel Hyper-Threading Technology Itanium processor. — Two times the number of OS threads per core — 2.5 times higher performance per watt.
  • Page 10 With double the performance of previous Intel Itanium processors, the Dual- Core Intel Itanium processor 9000 and 9100 series provides more reasons than ever to migrate your business-critical applications off RISC and mainframe systems and onto cost-effective Intel architecture servers.

  • Page 11: Introduction

    This strategy increases the synergy between hardware and software, and leads to greater overall performance. The Dual-Core Intel Itanium processor 9000 and 9100 series provides a 6-wide and 8- stage deep pipeline, running at up to 1.6 GHz. This provides a combination of abundant resources to exploit ILP as well as increased frequency for minimizing the latency of each instruction.

  • Page 12: Mixing Processors Of Different Frequencies And Cache Sizes

    Mixing Processors of Different Frequencies and Cache Sizes All Dual-Core Intel Itanium processor 9000 and 9100 series on the same system bus are required to have the same cache size (24 MB, 18 MB, 12 MB, 8 MB or 6 MB) and identical core frequency.

  • Page 13: Reference Documents

    ® Intel Itanium Processor Family System Abstraction Layer Specification ITP700 Debug Port Design Guide System Management Bus Specification Note: Contact your Intel representative or check http://developer.intel.com for the latest revision of the reference documents. § ® ® Dual-Core Intel Itanium...
  • Page 14 Introduction ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 15: Electrical Specifications

    Itanium Processor 9000 and 9100 Series System Bus Most Dual-Core Intel Itanium processor 9000 and 9100 series signals use the Itanium processor’s assisted gunning transceiver logic (AGTL+) signaling technology. The termination voltage, V , is generated on the baseboard and is the system bus high CTERM reference voltage.

  • Page 16: Itanium ® Processor System Bus Signal Groups

    Notes: ® ® 1. Signals will not be terminated on-die even when on-die termination (ODT) is enabled. See the Intel Itanium 2 Processor Hardware Developer’s Manual for further details. All system bus outputs should be treated as open drain signals and require a high-level source provided by the V supply.

  • Page 17: Signal Descriptions

    TERMB pins are terminated as indicated above. The TUNER3 pin will not be required for the majority of platforms supporting the Dual-Core Intel Itanium processor 9000 and 9100 series. The TUNER3 pin is used only in the case where A[21:17]# are driven to all zeros or all ones during the configuration cycles at reset.

  • Page 18: Package Specifications

    DC specifications for the AGTL+, PWRGOOD, HSTL clock, TAP port, system management, and LVTTL signals. Please refer to the ITP700 Debug Port Design Guide for the TAP connection signals’ DC specifications at the debug port. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 19: Agtl+ Signals Dc Specifications

    = 1.2 V +5%. IH, MAX OH, MAX 3. There is no internal pull-up. An external pull-up is always assumed. Max voltage tolerated at TDO is 1.5 V. 4. Per input pin. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 20: Smbus Dc Specifications

    BCLKp Frequency Figure 2-1 BCLK BCLKp Input Jitter Figure 2-1 jitter BCLKp High Time 1.69 1.88 2.06 Figure 2-1 high BCLKp Low Time 1.69 1.88 2.06 Figure 2-1 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 21: Generic Clock Waveform

    Generic Clock Waveform high jitter BCLKN rise fall period BCLKP Period Rise Time period rise Long Term Peak-to-Peak Jitter Fall Time fall jitter High Time Peak-to-Peak Swing high Low Time 000615 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 22: Maximum Ratings

    Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid static voltages or electric fields. ® ® Table 2-12. Dual-Core Intel Itanium Processor Absolute Maximum Ratings Symbol Parameter...

  • Page 23: System Bus Signal Quality Specifications And Measurement Guidelines

    Figure 2-3. System Bus Signal Waveform Exhibiting Overshoot/Undershoot 000588 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 24: Overshoot/Undershoot Pulse Duration

    (in nanoseconds) allowed. The pulse duration shown in the table refers to the period where either the maximum overshoot (for high phase) and undershoot (for low phase) occurred. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 25: Determining If A System Meets The Overshoot/Undershoot Specifications

    Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to GND. Ringback below V cannot be subtracted from overshoots/undershoots. CTERM Lesser undershoot does not allocate overshoot with longer duration or greater magnitude. All values specified by design characterization. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 26: Source Synchronous Agtl+ Signal Group Time-Dependent Overshoot/Undershoot Tolerance For 400-Mhz System Bus

    0.0297 0.0600 0.2989 1.55 –0.35 0.0093 0.0126 0.0191 0.0387 0.0980 0.1963 0.9822 –0.3 0.0303 0.0409 0.0625 0.1268 0.3178 0.6406 1.875 1.45 –0.25 0.3095 0.4191 0.6366 1.2965 1.875 1.875 1.875 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 27: Voltage Regulator Connector Signals

    If the VR cannot supply the voltages requested by the components in the processor package, then it must disable itself. Figure 2-4 shows the top view of the processor package power tab. See Table 2-19 power tab connector signals. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 28: Processors Power Tab Physical Layout

    Vid_cache [2] Vid_cache [3] Vid_cache [4] Vid_cache [5] A4 - N4 A5 - N5 Vcache A6 - N6 A7 - N7 Vcore A8 - N8 A9 - N9 Vcore ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 29 The VR shall provide a selectable output voltage controlled via multiple binary weighted Voltage Identification (VID) inputs. The VID value (high = 1; low = 0) is defined in Table 2-20. VID pins will be controlled by the processor. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 30: Processors Core Voltage Identification Code (Vcore And Vcache)

    0.725 1.1125 0.7125 1.0875 0.6875 1.075 0.675 1.0625 0.6625 1.05 0.65 1.0375 0.6375 1.025 0.625 1.0125 0.6125 0.9875 0.5875 0.975 0.575 0.9625 0.5625 0.95 0.55 0.9375 0.5375 0.925 0.525 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 31: System Bus Clock And Processor Clocking

    = Bus ratio signals must be asserted no later than RESET# = 2 BCLKs minimum, 3 BCLKs maximum = 4 BCLKs minimum = 2 BCLKs minimum, 3 BCLKs maximum 000859b ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 32: System Bus Reset And Configuration Timings For Warm Reset

    = Bus ratio signals must be asserted no later than RESET# = 2 BCLKs minimum, 3 BCLKs maximum = 4 BCLKs minimum = 2 BCLKs minimum, 3 BCLKs maximum 000777b ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 33: Recommended Connections For Unused Pins

    4. THRMALERT# should be pulled up to 3.3 V through a resistor. 5. With A[21;17] settings to all 0’ or all 1’s, please refer to Table 2-22 for proper connection. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 34: Tuner1/Tuner3 Translation Table

    A[21:17}# TUNER1 TUNER3 Bus (MHz) (V/ns) 1.92 0.82 Notes: 1. 0 = V , 1 = GND CTERM 2. 0 = Resistor not present, 1 = Resistor present § ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 35: Pinout Specifications

    Pinout Specifications Pinout Specifications This chapter describes the Dual-Core Intel Itanium processor 9000 and 9100 series signals and pinout. Note: The pins labeled “N/C” must remain unconnected. The processor uses a JEDEC standard pin naming convention. In this chapter, pin names are the actual names given to each physical pin of the processor.

  • Page 36: Pin/Signal Information Sorted By Pin Name

    Pinout Specifications Table 3-1 provides the Dual-Core Intel Itanium processor 9000 and 9100 series pin list in alphabetical order. Table 3-2 provides the Dual-Core Intel Itanium processor 9000 and 9100 series pin list by pin location. Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 1 of 15)
  • Page 37 D04# IN/OUT D005# D05# IN/OUT D006# D06# IN/OUT D007# D07# IN/OUT D008# D08# IN/OUT D009# D09# IN/OUT D010# D10# IN/OUT D011# D11# IN/OUT D012# D12# IN/OUT D013# D13# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 38 D48# IN/OUT D049# D49# IN/OUT D050# D50# IN/OUT D051# D51# IN/OUT D052# D52# IN/OUT D053# D53# IN/OUT D054# D54# IN/OUT D055# D55# IN/OUT D056# D56# IN/OUT D057# D57# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 39 D92# IN/OUT D093# D93# IN/OUT D094# D94# IN/OUT D095# D95# IN/OUT D096# D96# IN/OUT D097# D97# IN/OUT D098# D98# IN/OUT D099# D99# IN/OUT D100# D100# IN/OUT D101# D101# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 40 DEP4# IN/OUT DEP05# DEP5# IN/OUT DEP06# DEP6# IN/OUT DEP07# DEP7# IN/OUT DEP08# DEP8# IN/OUT DEP09# DEP9# IN/OUT DEP10# DEP10# IN/OUT DEP11# DEP11# IN/OUT DEP12# DEP12# IN/OUT DEP13# DEP13# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 41 AH25 AA02 AA20 AA24 AB01 AB03 AB05 AB07 AB09 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC02 AC24 AD01 AD03 AD05 AD07 AD09 AD11 AD13 AD15 AD17 AD19 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 42 Location AD21 AD23 AD25 AE02 AE24 AF01 AF05 AF07 AF09 AF11 AF13 AF15 AF17 AF19 AF21 AG02 AG04 AG06 AG08 AG10 AG12 AG14 AG16 AG18 AG20 AG22 AG24 AH01 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 43 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 8 of 15) System Bus Pin Name Input/Output Notes Signal Name Location ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 44 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 9 of 15) System Bus Pin Name Input/Output Notes Signal Name Location ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 45 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 10 of 15) System Bus Pin Name Input/Output Notes Signal Name Location ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 46 AC07 IGNNE# IGNNE# AG23 INIT# INIT# AF08 LINT0 AF22 LINT1 AF24 LOCK# LOCK# AE15 AB16 AC17 AC21 AD18 AE17 AG05 AG11 AG17 AG19 AG21 AH05 AH11 AH17 AH19 AH21 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 47 SMA1 SMBus signal SMA2 SMA2 SMBus signal SMSC SMSC SMBus signal SMSD SMSD IN/OUT SMBus signal SMWP SMWP SMBus signal STBN0# STBN0# IN/OUT STBN1# STBN1# IN/OUT STBN2# STBN2# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 48 VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 49 VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 50: Pin/Signal Information Sorted By Pin Location

    VCTERM VCCMON VCCMON VCTERM VCTERM SMA2 SMA2 SMBus signal SMA1 SMA1 SMBus signal VCTERM VCTERM SMWP SMWP SMBus signal VCTERM VCTERM VCTERM VCTERM 3.3V SMBus supply voltage Tuner[3] Tuner[3] ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 51 IN/OUT D070# D70# IN/OUT VCTERM VCTERM D099# D99# IN/OUT D097# D97# IN/OUT VCTERM VCTERM D004# D04# IN/OUT D003# D03# IN/OUT D005# D05# IN/OUT D037# D37# IN/OUT D034# D34# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 52 VCTERM D067# D67# IN/OUT STBP4# STBP4# IN/OUT VCTERM VCTERM D074# D74# IN/OUT D096# D96# IN/OUT VCTERM VCTERM STBP6# STBP6# IN/OUT D100# D100# IN/OUT D007# D07# IN/OUT STBN0# STBN0# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 53 D71# IN/OUT VCTERM VCTERM D072# D72# IN/OUT D079# D79# IN/OUT VCTERM VCTERM D101# D101# IN/OUT D108# D108# IN/OUT VCTERM VCTERM D107# D107# IN/OUT D011# D11# IN/OUT D012# D12# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 54 VCTERM VCTERM DEP05# DEP5# IN/OUT D047# D47# IN/OUT VCTERM VCTERM D078# D78# IN/OUT DEP09# DEP9# IN/OUT VCTERM VCTERM DEP08# DEP8# IN/OUT DEP12# DEP12# IN/OUT VCTERM VCTERM DEP13# DEP13# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 55 D056# D56# IN/OUT VCTERM VCTERM D052# D52# IN/OUT D081# D81# IN/OUT VCTERM VCTERM D088# D88# IN/OUT D082# D82# IN/OUT VCTERM VCTERM D112# D112# IN/OUT D116# D116# IN/OUT VCTERM VCTERM ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 56 D058# D58# IN/OUT VCTERM VCTERM STBN3# STBN3# IN/OUT D055# D55# IN/OUT VCTERM VCTERM D091# D91# IN/OUT STBN5# STBN5# IN/OUT VCTERM VCTERM D085# D85# IN/OUT D127# D127# IN/OUT VCTERM VCTERM ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 57 D031# D31# IN/OUT VCTERM VCTERM D063# D63# IN/OUT D060# D60# IN/OUT VCTERM VCTERM D059# D59# IN/OUT D092# D92# IN/OUT VCTERM VCTERM D089# D89# IN/OUT D090# D90# IN/OUT VCTERM VCTERM ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 58 A005# AA05#/EXF2# IN/OUT VCTERM VCTERM A009# AA09#/BE1# IN/OUT A018# AA18#/DID2# IN/OUT VCTERM VCTERM A016# AA16#/DID0# IN/OUT VCTERM VCTERM A028# AA28#/xTPRValue1# IN/OUT BNR# BNR# IN/OUT VCTERM VCTERM A027# AA27#/xTPRValue0# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 59 AA14#/BE6# IN/OUT A021# AA21#/DID5# IN/OUT A026# AA26#/AB26# IN/OUT A022# AA22#/DID6# IN/OUT A037# AA37#/AB37# IN/OUT A032# AA32#/ATTR0# IN/OUT A030# AA30#/xTPRValue3# IN/OUT A044# AA44#/AB44# IN/OUT A046# AA46#/AB46# IN/OUT A041# AA41#/AB41# IN/OUT ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 60 IN/OUT A033# AA33#/ATTR1# AA17 IN/OUT DBSY1# DBSY_C2# AA19 AA20 DRDY1# DRDY_C2# AA21 AP1# AP1# AA23 IN/OUT AA24 AP0# AP0# AA25 IN/OUT AB01 ID1# IDA1#/IP1# AB02 AB03 ID5# IDA5#/IDB5# AB04 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 61 AC19 N/C# AC21 BPM3# BPM3# AC23 IN/OUT AC24 BPM1# BPM1# AC25 IN/OUT AD01 ID0# IDA0#/IP0# AD02 AD03 ID4# IDA4#/IDB4# AD04 AD05 ID8# IDA8#/IDB8# AD06 AD07 RS1# RS1# AD08 AD09 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 62 OUTEN AF04 Power pod signal AF05 RSP# RSP# AF06 AF07 INIT# INIT# AF08 AF09 REQ1# WSNP#, D/C#/LEN1# AF10 IN/OUT AF11 REQ4# ASZ1#/DSZ1# AF12 IN/OUT AF13 TRDY# TRDY# AF14 AF15 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 63 AG21 AG22 IGNNE# IGNNE# AG23 AG24 THRMTRIP# THRMTRIP# AG25 Thermal trip AH01 TUNER[1] AH03 AH05 AH07 JTAG AH09 JTAG AH11 BCLKn BCLKN AH13 PWRGOOD PWRGOOD AH15 AH17 AH19 AH21 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 64 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 15 of 15) System Bus Pin Name Input/Output Notes Signal Name Location A20M# A20M# AH23 FERR# FERR# AH25 § ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 65: Mechanical Specifications

    Mechanical Specifications Mechanical Specifications This chapter provides the mechanical specifications of the Dual-Core Intel Itanium processor 9000 and 9100 series. Processor Package Dimensions Figure 4-1 through Figure 4-5 provide package mechanical drawings and dimensions of the processor. Table 4-1 Table 4-2 provide additional details on the package dimensions.

  • Page 66: Processor Package

    Mechanical Specifications Figure 4-1. Processor Package AH25 Side View Bottom View Package Top View Front View 001349 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 67: Package Height And Pin Dimensions

    Mechanical Specifications Table 4-1. Processor Package Dimensions Figure 4-2. Package Height and Pin Dimensions ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 68: Processor Package Mechanical Interface Dimensions

    Mechanical Specifications Table 4-2. Processor Package Mechanical Interface Dimensions ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 69: Processor Package Mechanical Interface Dimensions

    Mechanical Specifications Figure 4-3. Processor Package Mechanical Interface Dimensions ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 70: Processor Package Top-Side Components Height Dimensions

    Keepout zones indicate no components will be on the processor package. Figure 4-5. Processor Package Bottom-Side Components Height Dimensions Note: Keepout zones indicate no components will be on the processor package. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 71: Voltage Regulator (Mvr) To Processor Package Interface

    P Allowable torque on the package tip in Package loading in Y direction is not z axis allowed. Hence, zero torque in Z-axis ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 72: Package Marking

    The top-side mark is a laser marking on the IHS. Figure 4-7 shows the general location of the processor top-side mark that provides the following information: ® • Intel ® • Itanium Processor Family Legal Mark • Assembly Process Order (APO) Number •...

  • Page 73: Processor Bottom-Side Marking

    The processor bottom-side mark provides the following information: • Product ID • S-Spec • Finish Process Order (FPO) • 2D Matrix Mark ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 74: Processor Bottom-Side Marking Placement On Interposer

    Mechanical Specifications Figure 4-8. Processor Bottom-Side Marking Placement on Interposer Laser Marking Laser Marking 2D Matrix Mark (see notes) 2D Matrix Mark (see notes) SCALE SCALE § ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 75: Thermal Specifications

    (THIGH) or low temp (TLOW) registers on the sensor. Intel recommends using the upper temperature reference byte listed in the Processor Information ROM when programming the THIGH register (see Chapter 6 more details).

  • Page 76: Enhanced Thermal Management

    5.1.2 Enhanced Thermal Management ETM is a power and thermal protection feature. On the Dual-Core Intel Itanium processor 9000 and 9100 series, ETM uses power and thermal sensing devices on the die to monitor entry points, indicating dangerous operation exceeding the thermal or power specification.

  • Page 77: Itanium ® Processor Package Thermocouple Location

    This is the recommended location for placement of a thermocouple for case temperature measurement. ® Figure 5-2. Itanium Processor Package Thermocouple Location 24.13 45.00 Thermocouple Location All dimensions are measured in mm. Not to scale. 001103a § ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 78 Thermal Specifications ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 79: System Management Feature Specifications

    System Management Feature Specifications System Management Feature Specifications The Dual-Core Intel Itanium processor 9000 and 9100 series includes a system management bus (SMBus) interface. This chapter describes the features of the SMBus and SMBus components. System Management Bus 6.1.1 System Management Bus Interface The processor includes an Itanium processor family SMBus interface which allows access to several processor features.

  • Page 80: Logical Schematic Of Smbus Circuitry

    SMSD 3.3V SMA2 SMSC THRMALERT# 3.3V 3.3V Stuffing Options System Board System Board NOTE: 1. Actual implementation may vary. 2. For use in general understanding of the architecture. 000668b ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 81: Smbus Device Addressing

    SMBus master. Also, system management software must be aware of the processor select in the address for the thermal sensing device. ® ® Table 6-2. Thermal Sensing Device SMBus Addressing on the Dual-Core Intel Itanium Processor 9000 and 9100 series Address (Hex) Upper Address...

  • Page 82: Processor Information Rom

    System Management Feature Specifications ® ® Table 6-3. EEPROM SMBus Addressing on the Dual-Core Intel Itanium Processor 9000 and 9100 Series Memory Upper Read/ Processor Select Device Address Write Select Address Device Addressed (Hex) (SMA1) (SMA0) Bits 7–4 Bit 1...
  • Page 83 Package Package Revision Four 8-bit ASCII characters • 37h = N • 38h = E • 39h = 0 • 3Ah = 0 Substrate Revision Software 2-bit revision number ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 84 2h for dual-core processor Chain Reserved Reserved for future use Checksum 1 byte checksum Add up by byte and take 2’s complement. Other Reserved Reserved for future use 0000h ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 85: Scratch Eeprom

    Also available on the SMBus interface on the processor is an EEPROM which may be used for other data at the system vendor’s discretion (Intel will not be using the scratch EEPROM). The data in this EEPROM, once programmed, can be write-protected by asserting the active-high SMWP signal.

  • Page 86: Thermal Sensing Device

    8 bits Thermal Sensing Device The Dual-Core Intel Itanium processor 9000 and 9100 series thermal sensing device provides a means of acquiring thermal data from the processor. The accuracy of the thermal reading is expected to be better than ±5 °C. The thermal sensing device is composed of control logic, SMBus interface logic, a precision analog to digital converter, and a precision current source.

  • Page 87: Thermal Sensing Device Supported Smbus Transactions

    Command 7 bits 8 bits Table 6-11. Receive Byte SMBus Packet Address Read Data 7 bits 8 bits Table 6-12. ARA SMBus Packet Read Address 0001 100 1001 1011 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 88: Thermal Sensing Device Registers

    This value ranges from +127 to –128 decimal and is expressed as a two’s complement, eight-bit number. These registers are saturating, that is, values above 127 are represented at 127 decimal, and values below –128 are represented as –128 decimal. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 89: Thermal Limit Registers

    Standby mode control bit. If high, the device immediately stops converting, and enters standby mode. If low, the device converts in either one-shot or timer mode. 5–0 RESERVED Reserved for future use. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 90: Conversion Rate Register

    Table 6-16. Thermal Sensing Device Conversion Rate Register Register Contents Conversion Rate (Hz) 0.0625 0.125 0.25 08h to FFh Reserved for future use § ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 91: Signals Reference

    Signals Reference Signals Reference This appendix provides an alphabetical listing of all Dual-Core Intel Itanium 9000 and 9100 series processor system bus signals. The tables at the end of this appendix summarize the signals by direction: output, input, and I/O.

  • Page 92: Attr[3:0]# (I/O)

    BE[7:0]# (I/O) The BE[7:0]# signals are the byte-enable signals for partial transactions. They are driven by the request initiator during the second Request Phase clock on the Ab[15:8]# pins. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 93: Berr# (I/O)

    When the bus agent samples an asserted BERR# signal and BERR# sampling is enabled, the processor enters a Machine Check Handler. BERR# is a wired-OR signal to allow multiple bus agents to drive it at the same time. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 94: Binit# (I/O)

    The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. Table A-4 Table A-4 give the rotating interconnection between the processor and bus signals for both the 4P and 2P system bus topologies. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 95: Breq[3:0]# (I/O)

    BREQn# as soon as possible to release the bus. A symmetric owner stops issuing new requests that are not part of an existing locked operation on observing BPRI# asserted. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 96: Ccl# (I/O)

    The DEFER# signal is asserted by an agent to indicate that the transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the priority agent. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 97: Den# (I/O)

    Aa[25:16]# signals during the Deferred Reply transaction. This process enables the original requesting agent to make an identifier match with the original request that is awaiting completion. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 98: Dps# (I/O)

    EXF[4]# Reserved Reserved EXF[3]# SPLCK#/FCL# Split Lock / Flush Cache Line EXF[2]# OWN#/CCL# Memory Update Not Needed / Cache Cleanse EXF[1]# DEN# Defer Enable EXF[0]# DPS# Deferred Phase Supported ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 99: Fcl# (I/O)

    The Initialization (INIT#) signal triggers an unmasked interrupt to the processor. INIT# is usually used to break into hanging or idle processor states. Semantics required for platform compatibility are supplied in the PAL firmware interrupt service routine. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 100: Int (I)

    LINT[1] is typically software configured as NMI, a non-maskable interrupt.Both signals are asynchronous inputs. A.1.45 LOCK# (I/O) LOCK# is no connect and is ignored in the processor system environment. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 101: Nmi (I)

    REQ[5:0]# and ADS# are protected by parity RP#. All receiving agents observe the REQ[5:0]# signals to determine the transaction type and participate in the transaction as necessary, as shown in Table A-10. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 102: Reset# (I)

    A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high when all covered signals are high. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 103: Rsp# (I)

    STBp[7:0]# or STBn[7:0]#. The data is synchronized by DRDY#. Each strobe pair is associated with 16 data bus signals and two ECC signals as shown in Table A-11. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 104: Tck (I)

    TND# (I/O) The TLB Purge Not Done (TND#) signal is asserted to delay completion of a TLB Purge instruction, even after the TLB Purge transaction completes on the system bus. ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 105: Trdy# (I)

    Always BCLKn High — Control Always D/C# BCLKp System Bus Request Phase (Mem Rd) DEFER# BCLKp Snoop Snoop Phase DHIT# BCLKp System Bus IDS#+1 GSEQ# BCLKp Snoop Snoop Phase ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 106: Input/Output Signals (Single Driver)

    BCLKp System Bus ADS#+1 DSZ[1:0]# BCLKp System Bus ADS#+1 EXF[4:0]# BCLKp System Bus ADS#+1 FCL# BCLKp System Bus ADS#+1 LEN[2:0]# BCLKp System Bus ADS#+1 OWN# BCLKp System Bus ADS#+1 ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

  • Page 107: Input/Output Signals (Multiple Driver)

    Qualified BNR# BCLKp System Bus Always BERR# BCLKp Error Always BINIT# BCLKp Error Always HIT# BCLKp Snoop Snoop Phase HITM# BCLKp Snoop Snoop Phase TND# BCLKp Snoop Always § ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...
  • Page 108 Signals Reference ® ® Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet...

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