Ubox Pmon State - Counter/Control Pairs; U_Msr_Pmon_Ctl{1-0} Register - Field Definitions; U_Msr_Pmon_Ctr{1-0} Register - Field Definitions - Intel Xeon E5-2600 Series Monitoring Manual

2.2.3.2

UBox PMON state - Counter/Control Pairs

The following table defines the layout of the UBox performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter (.ev_sel, .umask). Additional control bits are provided to shape the incoming events (e.g.
.invert, .edge_det, .thresh) as well as provide additional functionality for monitoring software (.rst).
Table 2-2. U_MSR_PMON_CTL{1-0} Register – Field Definitions
Field
rsv
thresh
invert
en
rsv
rsv
edge_det
rst
umask
ev_sel
The UBox performance monitor data registers are 44-bit wide. Should a counter overflow (a carry out
from bit 43), the counter will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-3. U_MSR_PMON_CTR{1-0} Register – Field Definitions
Field
rsv
event_count
The Global UBox PMON registers also include a fixed counter that increments at UCLK for each cycle it
is enabled.
20
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
HW
Bits Attr Reset
Val
31:29 RV 0 Reserved (?)
28:24 RW 0 Threshold used in counter comparison.
23 RW 0 Invert comparison against Threshold.
0 - comparison will be 'is event increment >= threshold?'.
1 - comparison is inverted - 'is event increment < threshold?'
NOTE: .invert is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment when a 1
to 0 transition (i.e. falling edge) is detected.
22 RW 0 Local Counter Enable.
21:20 RV 0 Reserved. SW must write to 0 for proper operation.
19 RV 0 Reserved (?)
18 RW 0 When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event
is asserted.
NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
17 WO 0 When set to 1, the corresponding counter will be cleared to 0.
15:8 RW 0 Select subevents to be counted within the selected event.
7:0 RW 0 Select event to be counted.
HW
Bits Attr Reset
Val
63:44 RV 0 Reserved (?)
43:0 RW-V 0 44-bit performance event counter
Description
Description
Reference Number: 327043-001