10.4.3. Bist Result Boundary Scan Register; 10.4.4. Boundary Scan Register; Reset Behavior; Table 10-3. Device Id Register - Intel Pentium Pro Family Developer's Manual

VCC
Version
4 1
Size
xxxx 1
Binary
x 1
Hex

10.4.3. BIST Result Boundary Scan Register

Holds the results of BIST. It is loaded with a logical 0 on successful BIST completion.

10.4.4. Boundary Scan Register

Contains a cell for each defined Pentium Pro processor signal pin. The following is the bit order
of the cells in the register (left to right, top to bottom). The "Reserved" cells should be left alone.
PWRGOOD should never be driven low during TAP operation.
TDI -> CLK, PWRGOOD, Reserved, THERMTRIP#, STPCLK#, A20M#, FLUSH#,
INIT#, IGNNE#, FERR#,
SMI#, BPRI#, BNR#, BREQ[1:3]#,
DBSY#, HIT#, HITM#, RP#, BREQ[0]#, ADS#,
LINT[1:0], PICD[1:0], PICCLK, BP[3:2]#, BPM[1:0]#, PREQ#, PRDY#,
RESET#, BINIT#, DEP[0:7]#, D[63:0]#, Reserved-> TDO
10.5.

RESET BEHAVIOR

The TAP and its related hardware are reset by transitioning the TAP controller finite state ma-
chine into the Test-Logic-Reset state. Once in this state, all of the reset actions listed in Table
10-4 are performed. The TAP is completely disabled upon reset (i.e. by resetting the TAP, the
Pentium Pro processor will function as though the TAP did not exist). Note that the TAP does
not receive RESET#.
PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP)

Table 10-3. Device ID Register

Part Number
Product
Type Generation Model
6 4
000001 0110 00001
01 6 01
FRCERR, BERR#, IERR#, A[35:3]#, AP[0:1]#, RSP#,
REQ[4: 0]#, DEFER#, DRDY#, TRDY#,
Manufacturing
ID "1"
5 11 1
00000001001 1
09 1
LOCK#, RS[0:2]#, AERR#,
Entire Code
32
xxxx100000101100
0001000000010011
x82c1013
10-9