Test Data Registers; Bypass Register; Boundary-Scan Register - Intel PXA255 User Manual

9.4

Test Data Registers

The Test Data Registers are:
•

Bypass Register

•

Boundary-Scan Register

•
Device Identification (ID) Code Register
•
Data Specific Registers
9.4.1 Bypass Register
The Bypass register is a single-bit register that is selected as the path between TDI and TDO to
allow the device to be bypassed during boundary-scan testing. This allows for more rapid
movement of test data to and from other components on a board that are required to perform JTAG
test operations.
When the bypass, highz, or clamp instruction is the current instruction in the instruction register,
serial data is transferred from TDI to TDO in the Shift-DR state with a delay of one TCK cycle.
There is no parallel output from the bypass register.
A logic 0 is loaded from the parallel input of the bypass register in the Capture-DR state.
9.4.2 Boundary-Scan Register
The boundary-scan register consists of a serially connected set of cells around the periphery of the
device at the interface between the core logic and the system input/output pads. This register can be
used to isolate the pins from the core logic and then drive or monitor the system pins. The
connected boundary-scan cells make up a shift-register.
The boundary-scan register is selected as the register to be connected between TDI and TDO only
during the sample/preload and extest instructions. Values in the boundary-scan register are used,
but are not changed, during the clamp instruction.
In the normal (system) mode of operation straight-through connections between the core logic and
pins are maintained, and normal system operation is unaffected. Such is the case when the sample/
preload instruction is selected.
In test mode when extest is the currently selected instruction, values can be applied to the output
pins independently of the actual values on the input pins and core logic outputs. On the application
processor, all of the boundary-scan cells include update registers with the exception of the
nRESET_OUT and PWR_EN pins. In the case of the nRESET_OUT and PWR_EN pins, the
contents of the scan latches are not placed on the pins. This is to prevent a scan operation from
disabling power to the device and/or resetting external components.
The following pins are not part of the boundary-scan shift-register:
•
PEXTAL
•
PXTAL
•
TEXTAL
Intel® XScale™ Microarchitecture User's Manual
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9-5