6.2.26
PM_CS6 - Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 49.
PM_CS6 - Power Management Control/Status Register
Bit
Access
Default
Value
31:16
RO
0000h
15
RO
14:13
RO
12:9
RO
8
RW-S
7:4
RO
0000b
3
RO
2
RO
®
TM
Intel
Core
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
106
RST/
PWR
Core
Reserved
Not Applicable or Implemented. Hard wired to 0.
0b
Core
PME Status (PMESTS)
Indicates that this device does not support PMEB generation from
D3cold.
00b
Core
Data Scale (DSCALE)
Indicates that this device does not support the power
management data register.
0h
Core
Data Select (DSEL)
Indicates that this device does not support the power
management data register.
0b
Core
PME Enable (PMEE)
Indicates that this device does not generate PMEB assertion from
any D-state.0:PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.See
PM_CAP[15:11]
Core
Reserved
1b
Core
No Soft Reset (NSR)
When set to 1 this bit indicates that the device is transitioning
from D3hot to D0 because the power state commands do not
perform an internal reset. Config context is preserved. Upon
transition no additional operating sys intervention is required to
preserve configuration context beyond writing the power state
bits.
When clear the devices do not perform an internal reset upon
transitioning from D3hot to D0 via software control of the power
state bits.
Regardless of this bit, the devices that transition from a D3hot to
D0 by a system or bus segment reset will return to the device
state D0 un-initialized with only PME context preserved if PME is
supported and enabled.
0b
Core
Reserved
Processor Configuration Registers
0/6/0/PCI
84-87h
00000008h
RO; RW-S; RW
32 bits
Description
®
®
Celeron
Processor P4505, U3405 Series
August 2010
Document Number: 323178-003
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