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3.12.5.1
Local PCI Interrupts
Local interrupts from the PCI 9060 are signalled to the i960 processor on XINT0 for Cx, Hx, and Jx
processors, and INT2 for the Sx and Kx. Local PCI interrupts may be generated by self-test completion
(BIST), either of the DMA channels, the PCI-to-Local Doorbell Register, or LSERR. Each condition
has separate interrupt enable bits in the Interrupt Control and Status Register (E8H). DMA and doorbell
interrupts are discussed separately in the following subsections. The BIST interrupt can be generated by
local test code by setting bit 6 of the PCI Configuration BIST Register (0FH), and is typically used by
i960-side diagnostics to indicate completion.
LSERR can be asserted by the PCI 9060 when it detects a target abort or master abort while acting as a
PCI slave or PCI master. LSERR can also be triggered by the PCI 9060 when a PCI parity error occurs
during a master or slave transfer. Bits 0 and 1 of the Interrupt Control and Status Register (E8H) are
used to enable this local interrupt. LSERR is signalled to the Cx, Jx, and Hx processors on XINT2, and
to Sx and Kx processors on the PCI 9060 interrupt line INT2.
Field
Enable Local bus LSERR: 0 - disable; 1 - enable the PCI 9060 to assert LSERR
0
interrupt output when the PCI bus Target Abort or Master Abort status bit is set in the
PCI Status Configuration Register.
Enable Local bus LSERR when a PCI parity error occurs during a PCI 9060 Master
1
Transfer or a PCI 9060 Slave access.
Generate PCI bus SERR. When this bit is 0, setting it (writing a 1) generates a PCI bus
2
SERR.
7:3
Not Used
8
PCI interrupt enable: 0 - disable PCI interrupts; 1 - enable PCI interrupts.
PCI doorbell interrupt enable: 0 - disable doorbell interrupts; 1 - enable doorbell
interrupts.
9
Used in conjunction with PCI interrupt enable. Clear the doorbell interrupt bits that
cause the interrupt to clear the interrupt.
PCI Abort interrupt enable: 0 - disable; 1 - enable a master abort or master detect of a
target abort to generate a PCI interrupt.
10
Used in conjunction with PCI interrupt enable. Clear the abort status bits to clear the
PCI interrupt.
PCI local interrupt enable: 0- disable; 1 - enable a local interrupt input to generate a PCI
interrupt.
11
Used in conjunction with PCI interrupt enable. Clear the local bus cause of the interrupt
to clear the interrupt.
Table 3-33. Interrupt Control/Status
Description
HARDWARE REFERENCE
(Sheet 1 of 2)
Read
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Value
after
Reset
(Cold PC
Reset)
0
0
0
0
1
0
0
0
3-29
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