Pid Pci Memory-Mapped Registers; Memory-Mapped Register Summary; I/O Select Register Format - Intel 460GX Software Developer’s Manual

15:8
7:0
2.6.2

PID PCI Memory-mapped Registers

The PID uses two 32-bit memory-mapped registers to provide the indirect addressing access to its
(x)APIC interrupt redirection registers as well as to its ID, version, and arbitration ID registers. The
memory-mapped registers are placed at default addresses of FEC0_0000h, FEC0_0010h, and
FEC0_0040h for (x)APIC compatibility.
The I/O select register is used to provide the index of the internal register being accessed. The
register being accessed is determined by bits 7 through 0 of this register. The I/O window register is
used to provide/receive data associated with the access.
Table 2-2
Note: The default base address FEC00 which is mapped to A[31:12] can be changed by reprogramming
the (x)APIC base address register via PCI configuration space access.
Table 2-2. Memory-Mapped Register Summary
Address
FEC00000h
FEC00010h
FEC00040h
2.6.2.1 I/O Register Select Register (FEC00000h)
The I/O register select register selects which indirect access register appears in the I/O window
register where it can be manipulated by software. The selector values for the indirect access
registers are listed in
desired internal register. The contents of the selected 32-bit register can be manipulated via the I/O
window register. The I/O register select register is read/write by software and its default is listed in
Section 2.6.2.2. This starting address, where the I/O register select register and I/O window register
reside, can be relocated to a different address via the APIC base address register. The format of the
I/O register select register is shown in
Note: This register is defined as a 32-bit register, but only the lower eight bits are used. This register must
be accessed using 32-bit memory reads or writes. Bits 31 through 8 should be set to 0s.
Table 2-3. I/O Select Register Format
Register Offset: FEC00000hDefault Value: [00000000h]Attribute: Read/Write
Bit(s)
31:8
7:0
Intel® 460GX Chipset Software Developer's Manual
XTPR 1
These bits represent the external task priority for symmetric agent ID 01h.
XTPR 0
These bits represent the external task priority for symmetric agent ID 00h.
summarizes the memory-mapped registers. Detailed descriptions of each register follow.
I/O Register Select Register
I/O Window Register
(x)APIC EOI Register
Section 2.6.3. Software programs bits 7 through 0 of this register to select the
Name
Reserved These 24 bits are reserved.
REGISTER These eight bits provide the address offset of the internal 32-bit register. This
ADDRESS number is used to select consecutive 32-bit internal registers via the I/O
window register. Described in
Name
Table 2-3.
Description
Section 2.6.2.2
Register Descriptions
Access Default Value
R/W 00000000h
R/W 00000000h
R/W 00000000h
is 64-bit register access.
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