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I7-900 DESKTOP PROCESSOR - VOLUME 2
INTEL I7-900 DESKTOP PROCESSOR - VOLUME 2 Manuals
Manuals and User Guides for INTEL I7-900 DESKTOP PROCESSOR - VOLUME 2. We have
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INTEL I7-900 DESKTOP PROCESSOR - VOLUME 2 manual available for free PDF download: Datasheet
INTEL I7-900 DESKTOP PROCESSOR - VOLUME 2 Datasheet (98 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 0.56 MB
Table of Contents
Table of Contents
3
Revision History
9
1 Introduction
11
Terminology
11
Processor Terminology
11
References
13
2 Register Description
15
Register Terminology
15
Platform Configuration Structure
16
Device Mapping
17
Functions Specifically Handled by the Processor
17
Detailed Configuration Space Maps
18
Device 0, Function 0: Generic Non-Core Registers
18
Device 0, Function 1: System Address Decoder Registers
19
Device 2, Function 0: Intel QPI Link 0 Registers
20
Device 2, Function 1: Intel QPI Physical 0 Registers
21
Device 3, Function 0: Integrated Memory Controller Registers
22
Device 3, Function 1: Target Address Decoder Registers
23
Device 4, Function 0: Integrated Memory Controller Channel
24
Control Registers
24
Device 4, Function 1: Integrated Memory Controller Channel
25
Address Registers
25
Device 4, Function 2: Integrated Memory Controller Channel
26
Rank Registers
26
Device 4, Function 3: Integrated Memory Controller Channel
27
Thermal Control Registers
27
Device 5, Function 0: Integrated Memory Controller Channel
28
Control Registers
28
Device 5, Function 1: Integrated Memory Controller Channel
29
Address Registers
29
Device 5, Function 2: Integrated Memory Controller Channel
30
Rank Registers
30
Device 5, Function 3: Integrated Memory Controller Channel
31
Thermal Control Registers
31
Device 6, Function 0: Integrated Memory Controller Channel
32
Control Registers
32
Device 6, Function 1: Integrated Memory Controller Channel
33
Address Registers
33
Device 6, Function 2: Integrated Memory Controller Channel
34
Rank Registers
34
Device 6, Function 3: Integrated Memory Controller Channel
35
Thermal Control Registers
35
PCI Standard Registers
36
VID - Vendor Identification Register
36
DID - Device Identification Register
36
RID - Revision Identification Register
37
CCR - Class Code Register
37
HDR - Header Type Register
38
SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register
38
PCICMD - Command Register
39
PCISTS - PCI Status Register
40
SAD - System Address Decoder Registers
41
Sad_Pam0123
41
Sad_Pam456
43
Sad_Hen
44
Sad_Smram
44
Sad_Pciexbar
45
Sad_Dram_Rule_0, Sad_Dram_Rule_1, Sad_Dram_Rule_2
45
Sad_Dram_Rule_3
45
Sad_Dram_Rule_4, Sad_Dram_Rule_5
45
Sad_Dram_Rule_6, Sad_Dram_Rule_7
45
Sad_Interleave_List_0, Sad_Interleave_List_1
46
Sad_Interleave_List_2, Sad_Interleave_List_3
46
Sad_Interleave_List_4, Sad_Interleave_List_5
46
Sad_Interleave_List_6, Sad_Interleave_List_7
46
Intel QPI Link Registers
47
Qpi_Qpilcl_L0, Qpi_Qpilcl_L1
47
Integrated Memory Controller Control Registers
47
Mc_Control
47
Mc_Status
49
Mc_Smi_Spare_Dimm_Error_Status
50
Mc_Smi_Spare_Cntrl
51
Mc_Reset_Control
51
Mc_Channel_Mapper
52
Mc_Max_Dod
53
Mc_Rd_Crdt_Init
54
Mc_Crdt_Wr_Thld
55
Mc_Scrubaddr_Lo
55
Mc_Scrubaddr_Hi
56
TAD - Target Address Decoder Registers
57
Tad_Dram_Rule_0, Tad_Dram_Rule_1
57
Tad_Dram_Rule_2, Tad_Dram_Rule_3
57
Tad_Dram_Rule_4, Tad_Dram_Rule_5
57
Tad_Dram_Rule_6, Tad_Dram_Rule_7
57
Tad_Interleave_List_0, Tad_Interleave_List_1
58
Tad_Interleave_List_2, Tad_Interleave_List_3
58
Tad_Interleave_List_4, Tad_Interleave_List_5
58
Tad_Interleave_List_6, Tad_Interleave_List_7
58
Integrated Memory Controller Channel Control Registers
59
Mc_Channel_0_Dimm_Reset_Cmd
59
Mc_Channel_1_Dimm_Reset_Cmd
59
Mc_Channel_2_Dimm_Reset_Cmd
59
Mc_Channel_0_Dimm_Init_Cmd
60
Mc_Channel_1_Dimm_Init_Cmd
60
Mc_Channel_2_Dimm_Init_Cmd
60
Mc_Channel_0_Dimm_Init_Params
61
Mc_Channel_1_Dimm_Init_Params
61
Mc_Channel_2_Dimm_Init_Params
61
Mc_Channel_0_Dimm_Init_Status
62
Mc_Channel_1_Dimm_Init_Status
62
Mc_Channel_2_Dimm_Init_Status
62
Mc_Channel_0_Ddr3Cmd
63
Mc_Channel_1_Ddr3Cmd
63
Mc_Channel_2_Ddr3Cmd
63
Mc_Channel_0_Refresh_Throttle_Support
64
Mc_Channel_1_Refresh_Throttle_Support
64
Mc_Channel_2_Refresh_Throttle_Support
64
Mc_Channel_0_Mrs_Value_0_1
64
Mc_Channel_1_Mrs_Value_0_1
64
Mc_Channel_2_Mrs_Value_0_1
64
Mc_Channel_0_Mrs_Value_2
65
Mc_Channel_1_Mrs_Value_2
65
Mc_Channel_2_Mrs_Value_2
65
Mc_Channel_0_Rank_Present
65
Mc_Channel_1_Rank_Present
65
Mc_Channel_2_Rank_Present
65
Mc_Channel_0_Rank_Timing_A Mc_Channel_1_Rank_Timing_A Mc_Channel_2_Rank_Timing_A
66
Mc_Channel_0_Rank_Timing_B Mc_Channel_1_Rank_Timing_B Mc_Channel_2_Rank_Timing_B
69
Mc_Channel_0_Bank_Timing
70
Mc_Channel_1_Bank_Timing
70
Mc_Channel_2_Bank_Timing
70
Mc_Channel_0_Refresh_Timing
70
Mc_Channel_1_Refresh_Timing
70
Mc_Channel_2_Refresh_Timing
70
Mc_Channel_0_Cke_Timing Mc_Channel_1_Cke_Timing
71
Mc_Channel_2_Cke_Timing
71
Mc_Channel_0_Zq_Timing
71
Mc_Channel_2_Zq_Timing
71
Mc_Channel_0_Rcomp_Params
72
Mc_Channel_1_Rcomp_Params
72
Mc_Channel_2_Rcomp_Params
72
Mc_Channel_0_Odt_Params1
72
Mc_Channel_1_Odt_Params1
72
Mc_Channel_2_Odt_Params1
72
Mc_Channel_0_Odt_Params2
73
Mc_Channel_1_Odt_Params2
73
Mc_Channel_2_Odt_Params2
73
Mc_Channel_0_Odt_Matrix_Rank_0_3_Rd Mc_Channel_1_Odt_Matrix_Rank_0_3_Rd Mc_Channel_2_Odt_Matrix_Rank_0_3_Rd
73
Mc_Channel_0_Odt_Matrix_Rank_0_3_Wr Mc_Channel_1_Odt_Matrix_Rank_0_3_Wr Mc_Channel_2_Odt_Matrix_Rank_0_3_Wr
74
Mc_Channel_0_Odt_Matrix_Rank_4_7_Rd Mc_Channel_1_Odt_Matrix_Rank_4_7_Rd Mc_Channel_2_Odt_Matrix_Rank_4_7_Rd
74
Mc_Channel_0_Odt_Matrix_Rank_4_7_Wr Mc_Channel_1_Odt_Matrix_Rank_4_7_Wr Mc_Channel_2_Odt_Matrix_Rank_4_7_Wr
74
Mc_Channel_0_Waq_Params
75
Mc_Channel_1_Waq_Params
75
Mc_Channel_2_Waq_Params
75
Mc_Channel_0_Maintenance_Ops
76
Mc_Channel_0_Scheduler_Params
76
Mc_Channel_1_Maintenance_Ops
76
Mc_Channel_1_Scheduler_Params
76
Mc_Channel_2_Maintenance_Ops
76
Mc_Channel_2_Scheduler_Params
76
Mc_Channel_0_Rx_Bgf_Settings
77
Mc_Channel_0_Tx_Bg_Settings
77
Mc_Channel_1_Tx_Bg_Settings
77
Mc_Channel_2_Rx_Bgf_Settings
77
Mc_Channel_2_Tx_Bg_Settings
77
Mc_Channel_0_Ew_Bgf_Offset_Settings
78
Mc_Channel_0_Ew_Bgf_Settings
78
Mc_Channel_0_Round_Trip_Latency
78
Mc_Channel_1_Ew_Bgf_Offset_Settings
78
Mc_Channel_1_Ew_Bgf_Settings
78
Mc_Channel_1_Round_Trip_Latency
78
Mc_Channel_2_Ew_Bgf_Offset_Settings
78
Mc_Channel_2_Ew_Bgf_Settings
78
Mc_Channel_2_Round_Trip_Latency
78
Mc_Channel_0_Pagetable_Params1
79
Mc_Channel_0_Pagetable_Params2
79
Mc_Channel_1_Pagetable_Params1
79
Mc_Channel_1_Pagetable_Params2
79
Mc_Channel_2_Pagetable_Params1
79
Mc_Channel_2_Pagetable_Params2
79
Mc_Tx_Bg_Cmd_Data_Ratio_Settings_Ch2
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch0
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch1
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch2
80
Mc_Tx_Bg_Data_Offset_Settings_Ch0
80
Mc_Tx_Bg_Data_Offset_Settings_Ch1
80
Mc_Tx_Bg_Data_Offset_Settings_Ch2
80
Mc_Channel_0_Addr_Match
81
Mc_Channel_1_Addr_Match
81
Mc_Channel_2_Addr_Match
81
Mc_Channel_0_Ecc_Error_Inject
82
Mc_Channel_0_Ecc_Error_Mask
82
Mc_Channel_1_Ecc_Error_Inject
82
Mc_Channel_1_Ecc_Error_Mask
82
Mc_Channel_2_Ecc_Error_Inject
82
Mc_Channel_2_Ecc_Error_Mask
82
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