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2.8.10
GTTMMADR—Graphics Translation Table, Memory Mapped
Range Address Register
This register requests allocation for the combined Graphics Translation Table
Modification Range and Memory Mapped Range. The range requires 4 MB combined for
MMIO and Global GTT aperture, with 2MB of that used by MMIO and 2 MB used by GTT.
GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address will be the
same as GTTMMADR.
For the Global GTT, this range is defined as a memory BAR in graphics device
configuration space. It is an alias into which software is required to write Page Table
Entry values (PTEs). Software may read PTE values from the global Graphics
Translation Table (GTT). PTEs cannot be written directly into the global GTT memory
area.
The device snoops writes to this region in order to invalidate any cached translations
within the various TLBs implemented on-chip.
The allocation is for 4 MB and the base address is defined by bits 38:22.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
63:39
38:22
21:4
3
2:1
0
134
0/2/0/PCI
10–17h
0000000000000004h
RW, RO
64 bits
Reset
RST/
Attr
Value
PWR
FLR,
RW
0000000h
Uncore
FLR,
RW
00000h
Uncore
RO
00000h
Uncore
RO
0b
Uncore
RO
10b
Uncore
RO
0b
Uncore
Processor Configuration Registers
Description
Reserved for Memory Base Address (RSVDRW)
Must be set to 0 since addressing above 512 GB is not supported.
Memory Base Address (MBA)
Set by the OS, these bits correspond to address signals [38:22].
4 MB combined for MMIO and Global GTT table aperture (2 MB for
MMIO and 2 MB for GTT).
Address Mask (ADM)
Hardwired to 0s to indicate at least 4 MB address range.
Prefetchable Memory (PREFMEM)
Hardwired to 0 to prevent prefetching.
Memory Type (MEMTYP)
00 = To indicate 32 bit base address
01 = Reserved
10 = To indicate 64 bit base address
11 = Reserved
Memory/IO Space (MIOS)
Hardwired to 0 to indicate memory space.
Datasheet, Volume 2
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