Ready Signal Set-Up Time; Request/Grant L In E; Non-Maskable Interrupt Line And Interrupt Line; Non-Maskable Interrupts And Program Stepping - Intel l2ICE User Manual

READY Signal Set-U p Tim e
The BTHRDY (both READY) pseudo-variable ANDs the user's processor READY signal with
the 8086/8088 probe's ready signal. When BTHRDY is TRUE, the 8086/8088 probe's READY
signal must be set up .3 nanoseconds before the rising edge of T2, as shown in Figure 4-1.
If the probe processor's READY signal is not set up .3 nanoseconds before the rising edge of
T2, the signal is missed and the result of the logical AND is false. This causes an additional
wait-state in a normally not-READY system and no wait-states in a normally READY system.
Set-up time is normal when BTHRDY is FALSE.
R equest/G rant Line
The internal 8087 coprocessor uses the request/grant (RQ/GT1) line. You cannot connect bus
masters in a daisy chain on the RQ/GT1 line when you use an internal 8087.
N on-M askable Interrupt Line and Interrupt Line
If a non-maskable interrupt (NMI) and an interrupt (INTR) are asserted at the same time, the
PICE system starts to service the INTR first. This results in additional latency while the stack
operations and interrupt acknowledge cycles occur. The NMI is serviced after the INTR vector
and initial stack activity are complete. The INTR service is completed after the NMI is
serviced.
N on-M askable Interrupts and Program Stepping
The 8086/8088 probe ignores NMIs when stepping through a user program with the ISTEP
command. The following GO command, which steps through 10 consecutive break locations,
enables you to step through programs while recognizing NMIs.
COUNT 10
ENO

Synchronization betw een the Prototype and the Probe

When the probe is executing code from high-speed (HS) memory but the user prototype ex­
pects memory with a different access time in the same address space, the user's bus control
logic can get out of synchronization with the probe. A solution is to set the BTHRDY pseudo­
variable to TRUE.
If the user prototype expects slow memory, another solution is to insert an appropriate number
of wait-states into the HS memory accesses.

U ser-A ccessible Test Points

The top of the buffer box has two user-accessible user test points. They are labeled SYNC
START/ and 87 INT.
4-4
GO Tit 0XXXX
The PICE™ System Personality Modules (Probes)