Os Timer Interface; Overview - Intel PXA27 Series Design Manual

OS Timer Interface

This chapter describes procedures for interfacing the OS Timer controller to Intel
Processor Family (PXA27x processor).
22.1

Overview

The operating system timers block provides a set of timer channels that allow software to generate
timed interrupts (or wakeup events). In the PXA27x processor, these interrupts are generated by
two sets of timer channels:
•
One set provides one counter and four match registers and is clocked from a 3.25-MHz clock.
This block maintains the four Intel
•
The other set (additional to the Intel
match registers and clocked from any of the following:
— 32.768 KHz timer lock
— 13 MHz clock
— An externally supplied clock that provides a wide range of timer resolutions
All references to registers are documented in the Intel
Manual unless otherwise noted.
22.2 Signals
See Table 22-1
Table 22-1. OS Timer Interface Signals
Name
EXT_SYNC<0>
EXT_SYNC<1>
CHOUT<0>
CHOUT<1>
®
Intel PXA27x Processor Family Design Guide
®
®
for the list of signals used to interface to the OS Timer.
Type
External Sync 0
Input
This input provides a reset for the OS Timer channels
enabled for use
External Sync 1
Input
This input provides a reset for the OS Timer channels
enabled for use
Channel Out 0
Output
Periodic clock output from OS Timer channel 11
Channel Out 1
Output
Periodic clock output from OS Timer channel 10
PXA25x processor compatible timer channels.
PXA25x processor) provides eight counters and eight
®
PXA27x Processor Family Developers
Description
22
®
PXA27x
II:22-1