Intel 80C186EC Manuals

Manuals and User Guides for Intel 80C186EC. We have 2 Intel 80C186EC manuals available for free PDF download: User Manual, Manual

Intel 80C186EC User Manual

Intel 80C186EC User Manual (515 pages)

Brand: Intel | Category: Computer Hardware | Size: 2.55 MB

Table of Contents

Table of Contents
4
Chapter 1 Introduction

25
- How to Use this Manual
  25
- Related Documents
  26
- Electronic Support Systems
  27
- Technical Support
  29
- Product Literature
  30
- Training Classes
  30
Chapter 2 Overview of the 80C186 Family Architecture

32
- Architectural Overview
  34
  - Execution Unit
    35
  - Bus Interface Unit
    36
  - General Registers
    37
  - Segment Registers
    38
  - Instruction Pointer
    39
  - Flags
    40
  - Memory Segmentation
    41
  - Processor Status Word
    42
  - Logical Addresses
    43
  - Dynamically Relocatable Code
    46
  - 2.1.10 Stack Implementation
    48
  - 2.1.11 Reserved Memory and I/O Space
    48
- Software Overview
  50
  - Instruction Set
    50
    
    Data Transfer Instructions
    51
    
    Arithmetic Instructions
    52
    
    Bit Manipulation Instructions
    54
    
    String Instructions
    55
    
    Program Transfer Instructions
    56
    
    Processor Control Instructions
    60
  - Addressing Modes
    60
    
    Register and Immediate Operand Addressing Modes
    60
    
    Memory Addressing Modes
    61
    
    I/O Port Addressing
    69
    
    Data Types Used in the 80C186 Modular Core Family
    70
    
    Interrupts and Exception Handling
    72
    
    Non-Maskable Interrupts
    75
    
    Software Interrupts
    77
    
    Interrupt Response Time
    78
    
    Interrupt and Exception Priority
    79
    
    Address and Data Bus Concepts
    86
    
    Bit Data Bus
    90
    
    Memory and I/O Interfaces
    91
    
    Bit Bus Memory and I/O Requirements
    92
    
    Address/Status Phase
    95
    
    Data Phase
    98
    
    Idle States
    103
    
    Bus Cycles
    105
    
    Refresh Bus Cycles
    107
    
    Write Bus Cycles
    108
    
    Interrupt Acknowledge Bus Cycle
    111
    
    System Design Considerations
    113
    
    HALT Bus Cycle
    114
    
    Temporarily Exiting the HALT Bus State
    117
    
    Exiting HALT
    119
    
    System Design Alternatives
    121
    
    Buffering the Data Bus
    122
    
    Synchronizing Software and Hardware Events
    124
    
    Using a Locked Bus
    125
    
    Multi-Master Bus System Designs
    126
    
    HOLD Bus Latency
    127
    
    Refresh Operation During a Bus HOLD
    128
    
    Exiting HOLD
    130
    
    Bus Cycle Priorities
    131
    
    Peripheral Control Registers
    136
    
    Reserved Locations
    139
    
    F-Bus Operation
    140
    
    Writing the PCB Relocation Register
    141
    
    Considerations for the 80C187 Math Coprocessor Interface
    142
    
    Crystal Oscillator
    146
    
    Oscillator Operation
    147
    
    Selecting Crystals
    150
    
    Using an External Oscillator
    151
    
    Power Management
    155
    
    Idle Mode
    156
    
    Bus Operation During Idle Mode
    158
    
    Leaving Idle Mode
    159
    
    Example Idle Mode Initialization Code
    160
    
    Powerdown Mode
    161
    
    Entering Powerdown Mode
    162
    
    Leaving Powerdown Mode
    163
    
    Power-Save Mode
    164
    
    Entering Power-Save Mode
    165
    
    Leaving Power-Save Mode
    167
    
    Implementing a Power Management Scheme
    169
    
    Chip-Select Unit Features and Benefits
    172
    
    Chip-Select Unit Functional Overview
    173
    
    Programming
    176
    
    Initialization Sequence
    177
    
    Start Address
    181
    
    Enabling and Disabling Chip-Selects
    182
    
    Overlapping Chip-Selects
    183
    
    Memory or I/O Bus Cycle Decoding
    185
    
    Chip-Selects and Bus Hold
    186
    
    Example 2: Detecting Attempts to Access Guarded Memory
    191
    
    Refresh Control Unit
    194
    
    Refresh Control Unit 7.1 the Role of the Refresh Control Unit
    195
    
    Refresh Addresses
    197
    
    Refresh Bus Cycles
    198
    
    Programming the Refresh Control Unit
    200
    
    Refresh Base Address Register
    201
    
    Refresh Control Register
    202
    
    Refresh Address Register
    203
    
    Programming Example
    204
    
    Refresh Operation and Bus Hold
    206
    
    Interrupt Priority and Nesting
    213
    
    A Typical Interrupt Sequence Using the 8259A Module
    215
    
    Interrupt Requests
    218
    
    Spurious Interrupts
    219
    
    Default (Fixed) Priority
    220
    
    Changing the Default Priority: Automatic Rotation
    221
    
    Clearing the In-Service Bits: Non-Specific End-Of-Interrupt
    222
    
    Masking Interrupts
    223
    
    The Cascaded Interrupt Acknowledge Cycle: an Example
    225
    
    Master Cascade Configuration
    226
    
    Spurious Interrupts in a Cascaded System
    227
    
    Alternate Modes of Operation: Special Mask Mode
    228
    
    Alternate Modes of Operation: the Poll Command
    229
    
    Programming Sequence and Register Addressing
    230
    
    ICW1: Edge/Level Mode, Single/Cascade Mode
    232
    
    ICW2: Base Interrupt Type
    234
    
    ICW3: Cascaded Pins/Slave Address
    235
    
    The Operation Command Words
    239
    
    Special Mask Mode, Poll Mode and Register Reading: OCW3
    243
    
    Module Integration: the 80C186Ec Interrupt Control Unit
    245
    
    Directly Supported Internal Interrupt Sources
    246
    
    Indirectly Supported Internal Interrupt Sources
    247
    
    Using the Interrupt Request Latch Registers
    248
    
    Using the Interrupt Request Latch Registers to Debug Interrupt Handlers
    249
    
    Hardware Considerations with the Interrupt Control Unit
    251
    
    Interrupt Latency and Response Time
    252
    
    Ready Generation
    253
    
    The External INTA Cycle
    254
    
    Timing Constraints
    255
    
    Module Examples
    256
    
    Interrupt Control Unit
    257
    
    Functional Overview
    264
    
    Programming the Timer/Counter Unit
    269
    
    Timer 2 Control Register
    272
    
    Initialization Sequence
    274
    
    Clock Sources
    275
    
    Retriggering
    276
    
    Pulsed and Variable Duty Cycle Output
    277
    
    Enabling/Disabling Counters
    278
    
    Timer Interrupts
    279
    
    Synchronization and Maximum Frequency
    280
    
    The DMA Transfer
    290
    
    DMA Transfer Directions
    292
    
    External Requests
    293
    
    Source Synchronization
    294
    
    Internal Requests
    295
    
    Serial Communications Unit Transfers
    296
    
    Termination at Terminal Count
    297
    
    The Two-Channel DMA Module
    298
    
    DMA Module Integration
    301
    
    DMA Unit Structure
    302
    
    Programming the Dma Unit
    304
    
    Selecting Byte or Word Size Transfers
    308
    
    Dma Control Register
    309
    
    Dma Control Register
    310
    
    Selecting the Source of DMA Requests
    311
    
    Arming the DMA Channel
    312
    
    Programming the Transfer Count Options
    313
    
    Generating Interrupts on Terminal Count
    314
    
    Setting the Relative Priority of a Channel
    315
    
    Suspension of DMA Transfers Using the DMA Halt Bits
    316
    
    Hardware Considerations and the Dma Unit
    317
    
    DRQ Pin Timing Requirements
    318
    
    Generating a DMA Acknowledge
    319
    
    Asynchronous Communications
    330
    
    RX Machine
    331
    
    TX Machine
    333
    
    Modes 1, 3 and 4
    335
    
    Mode 2
    336
    
    Synchronous Communications
    337
    
    Programming
    338
    
    Baud Rates
    339
    
    Asynchronous Mode Programming
    342
    
    Modes 2 and 3 for Multiprocessor Communications
    343
    
    Programming in Mode 0
    347
    
    Mode 0 Timings
    349
    
    BCLK as Baud Timebase Clock
    350
    
    Mode 0 Example
    352
    
    Master/Slave Example
    353
    
    Using the Watchdog Timer as a System Watchdog
    364
    
    Reloading the Watchdog Timer down Counter
    366
    
    Watchdog Timer Reload Value
    367
    
    Initialization
    368
    
    Using the Watchdog Timer as a General-Purpose Timer
    369
    
    Watchdog Timer Registers
    371
    
    Initialization Example
    375
    
    Bidirectional Port
    380
    
    Output Port
    382
    
    Port 1 Organization
    385
    
    Port 3 Organization
    386
    
    Port Direction Register
    387
    
    Port Data Latch Register
    388
    
    Port Pin State Register
    389
    
    Initializing the I/O Ports
    390
    
    Programming Example
    391
    
    Availability of Math Coprocessing
    394
    
    The 80C187 Math Coprocessor
    395
    
    Data Transfer Instructions
    396

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Intel 80C186EC Manual

Intel 80C186EC Manual (57 pages)

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Brand: Intel | Category: Computer Hardware | Size: 1.61 MB

Table of Contents

Table of Contents
2
Introduction

4
80C186Ec Core Architecture

4
- Bus Interface Unit
  4
- Clock Generator
  4
80C186Ec Peripheral Architecture

5
- Programmable Interrupt Controllers
  7
- Timer Counter Unit
  7
- Serial Communications Unit
  7
- DMA Unit
  7
- Chip-Select Unit
  7
- I O Port Unit
  7
- Refresh Control Unit
  7
- Watchdog Timer Unit
  7
- Power Management Unit
  8
- 80C187 Interface (80C186EC Only)
  8
- ONCE Test Mode
  8
Package Information

8
- Prefix Identification
  8
- Pin Descriptions
  8
- Pinout
  15
- Package Thermal Specifications
  24
Electrical Specifications

25
- Absolute Maximum Ratings
  25
- Recommended Connections
  25
DC Specifications

26
- ICC Versus Frequency and Voltage
  29
- PDTMR Pin Delay Calculation
  29
Ac Specifications

30
- AC Characteristics 80C186EC25
  30
- AC Characteristics 80C186EC20
  31
- AC Characteristics 80L186EC13
  33
- AC Characteristics 80L186EC16
  34
- Relative Timings
  35
- Serial Port Mode 0 Timings
  36
Ac Test Conditions

37
Ac Timing Waveforms

37
Derating Curves

40
Reset

40
Bus Cycle Waveforms

43
Execution Timings

50
Instruction Set Summary

51
Errata

57
Revision History

57

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