D9.42 Trcitatbidr, Integration Atb Identification Register - ARM Cortex-A76 Core Technical Reference Manual

D9.42 TRCITATBIDR, Integration ATB Identification Register
The TRCITATBIDR sets the state of output pins, mentioned in the bit descriptions in this section.
Bit field descriptions
The TRCITATBIDR is a 32-bit register.
[31:7]
ID, [6:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCITATBIDR can be accessed through the external debug interface, offset
100798_0300_00_en
31
Reserved. Read undefined.
Drives the ATIDMn[6:0] output pins.
When a bit is set to 0, the corresponding output pin is LOW.
When a bit is set to 1, the corresponding output pin is HIGH.
The TRCITATBIDR bit values correspond to the physical state of the output pins.
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D9.42 TRCITATBIDR, Integration ATB Identification Register

Reserved
Figure D9-40 TRCITATBIDR bit assignments
reserved.
Non-Confidential
D9 ETM registers
7 6 0
ID
®
.
0xEE4
D9-552