Table 2-5 Exception Priority Order; Exception Priorities - ARM ARM7TDMI Technical Reference Manual

Programmer's Model
Address
0x00000010
0x00000014
0x00000018
0x0000001C
2.8.10

Exception priorities

2-22
Exception
Data Abort
Reserved
IRQ
FIQ
When multiple exceptions arise at the same time, a fixed priority system determines the
order in which they are handled. The priority order is listed in Table 2-5.
Some exceptions cannot occur together:
• The undefined instruction and SWI exceptions are mutually exclusive. Each
corresponds to a particular, non-overlapping, decoding of the current instruction.
• When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the
ARM7TDMI processor enters the Data Abort handler, and proceeds immediately
to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the
worst-case FIQ latency calculations in a system that uses aborts to support virtual
memory.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Table 2-4 Exception vectors (continued)
Mode on entry I state on entry
Abort Set
Reserved -
IRQ Set
FIQ Set

Table 2-5 Exception priority order

Priority Exception
Highest Reset
Data Abort
FIQ
IRQ
Prefetch Abort
Lowest Undefined instruction and SWI
F state on entry
Unchanged
-
Unchanged
Set
ARM DDI 0210C