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RM0401
13.8
RNG registers
The RNG is associated with a control register, a data register and a status register.
13.8.1
RNG control register (RNG_CR)
Address offset: 0x000
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value
Bit 5 CED: Clock error detection
The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is
enabled, i.e. to enable or disable CED the RNG must be disabled.
Bit 4 Reserved, must be kept at reset value.
Bit 3 IE: Interrupt Enable
Bit 2 RNGEN: True random number generator enable
Bits 1:0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
0: Clock error detection is enable
1: Clock error detection is disable
0: RNG Interrupt is disabled
1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or
CEIS='1' in the RNG_SR register.
0: True random number generator is disabled. Analog noise sources are powered off and
logic clocked by the RNG clock is gated.
1: True random number generator is enabled.
True random number generator (RNG)
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
CED
RM0401 Rev 3
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
IE
RNGEN
rw
rw
rw
17
16
Res.
Res.
1
0
Res.
Res.
265/771
268
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