ST Sound Terminal STA333W Manual
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ST Sound Terminal STA333W Manual

ST Sound Terminal STA333W Manual

2-channel high-efficiency digital audio system
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Features
Wide supply-voltage range (4.5 V - 20 V)
2 power output configurations
– 2 channels of binary PWM (stereo mode)
– 2 channels of ternary PWM (stereo mode)
PowerSSO-36 with exposed pad down
2 channels of 24-bit DDX
100-dB SNR and dynamic range
Selectable 32- to 192-kHz input sample rates
2
I
C control with selectable device address
Digital gain -80 dB to +48 dB in 0.5-dB steps
Software volume update
Individual channel and master gain/attenuation
Individual channel and master software and
hardware mute
Independent channel volume bypass
Automatic zero-detect mute
Automatic invalid input detect mute
2
2-channel I
S input data Interface
Selectable clock input ratio
Input channel mapping
Automatic volume control for limiting maximum
power
96-kHz internal processing sample rate, 24-bit
precision
Advanced AM interference frequency
switching and noise suppression modes
Thermal-overload and short-circuit protection
embedded
Video application: 576 * f
Table 1.
Device summary
Order code
STA333W
STA333W13TR
January 2010
2-channel high-efficiency digital audio system
®
input mode support
S
Package
PowerSSO-36 EPD
PowerSSO-36 EPD
Doc ID 13365 Rev 2
Applications
LCD
DVD
Cradle
Digital speaker
Wireless-speaker cradle
Description
The STA333W is an integrated circuit comprising
digital audio processing, digital amplifier control
®
and DDX
power output stage to create a high-
power, single-chip DDX
amplification with high quality and high efficiency.
The STA333W power section consists of four
independent half-bridges stages. These can be
configured via digital control to operate in different
modes. 2 channels can be provided by two full
bridges, providing up to 20 W + 20 W of power.
Also provided in the STA333W are new advanced
AM radio interference reduction modes. The serial
audio data input interface accepts all possible
formats, including the popular I
®
channels of DDX
processing are provided.
The STA333W is part of the Sound Terminal™
family that provides full digital audio streaming to
the speaker offering cost effectiveness, low power
dissipation and sound enrichment.
Tube
Tape and reel
STA333W
Sound Terminal™
PowerSSO-36 package
with exposed
pad down (EPD)
®
solution for all-digital
2
S format. Three
Packaging
www.st.com
1/49
49

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  • Page 1: Table 1. Device Summary

    Video application: 576 * f input mode support dissipation and sound enrichment. Table 1. Device summary Order code Package Packaging STA333W PowerSSO-36 EPD Tube STA333W13TR PowerSSO-36 EPD Tape and reel January 2010 Doc ID 13365 Rev 2 1/49 www.st.com...

  • Page 2: Table Of Contents

    Contents STA333W Contents Block diagram ..........7 Pin description .
  • Page 3 STA333W Contents 5.4.1 Current address byte read ........19 5.4.2 Current address multi-byte read .
  • Page 4 Contents STA333W Package mechanical data ........45 Trademarks and other acknowledgements .
  • Page 5 STA333W List of tables List of tables Table 1. Device summary ............1 Table 2.
  • Page 6 List of figures STA333W List of figures Figure 1. Block diagram ............7 Figure 2.

  • Page 7: Block Diagram

    STA333W Block diagram Block diagram Figure 1. Block diagram Protection current/thermal Channel interface Channel Logic Power control Volume control Channel Regulators Channel Bias Digital DSP Power Doc ID 13365 Rev 2 7/49...

  • Page 8: Pin Description

    Pin description STA333W Pin description Pin out Figure 2. Pin connection (package top view) GND_SUB VDD_DIG GND_DIG TEST_MODE VCC_REG INT_LINE OUT2B RESET GND2 VCC2 LRCKI OUT2A BICKI OUT1B VCC1 GND_PLL GND1 FILTER_PLL OUT1A VDD_PLL GND_REG PWRDN exposed pad (down) VDD_REG Connect to ground GND_DIG CONFIG...

  • Page 9: Table 2

    STA333W Pin description Table 2. Pin description (continued) Number Type Name Description OUT1B Output half bridge 1B VCC1 Power positive supply GND1 Power negative supply OUT1A Output half bridge 1A GND_REG Internal ground reference VDD_REG Internal 3.3-V reference voltage CONFIG Paralleled mode command N.C.

  • Page 10: Thermal Data

    Pin description STA333W Thermal data Table 3. Thermal data Symbol Parameter Unit Thermal resistance junction to case (thermal pad) °C/W Th(j-case) Thermal-shutdown junction temperature °C Thermal-warning temperature °C Thermal-shutdown hysteresis °C 10/49 Doc ID 13365 Rev 2...

  • Page 11: Electrical Specification

    STA333W Electrical specification Electrical specification Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Unit Analog supply voltage (pins VCCx) Digital supply voltage (pins VDD_DIG) Logic input interface -0.3 Operating junction temperature °C Storage temperature °C Warning: Stresses beyond those listed in Table 4: Absolute maximum ratings may cause permanent damage to the device.

  • Page 12: Electrical Specifications - Digital Section

    Electrical specification STA333W Electrical specifications - digital section Table 6. Electrical characteristics for digital section Symbol Parameter Conditions Unit = 0 V ±10 µA Input current, no pull-up or pull-down resistor = 3.6 V ±10 µA 0.2 * Low-level input voltage 0.8 * High-level input voltage 0.4 *...
  • Page 13 STA333W Electrical specification Table 7. Electrical specifications for power section (continued) Symbol Parameter Conditions Unit Supply voltage Supply current from V PWRDN = 0 µA power down PCM input signal = -60 dBfs Supply current from V Switching frequency = operation 384 kHz No LC filters...

  • Page 14: Power-On/Off Sequences

    Electrical specification STA333W Power-on/off sequences The power-on/off sequences shown in Figure 3 Figure 4 below ensure a pop-free turn on and turn off. Figure 3. Power-on sequence No specific VCC and VDD_DIG turn-on sequence is required Don’t care Don’t care VDD_Dig VDD_Dig VDD_DIG...

  • Page 15: Testing

    STA333W Electrical specification Testing Figure 5. Test circuit OUTxY (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc Duty cycle = 50% OUTxY R 8Ω INxY V67 = vdc = Vcc/2 D03AU1458 Figure 6. Current dead-time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) Duty cycle=A Duty cycle=B DTout(A)

  • Page 16: Functional Description

    Functional description STA333W Functional description Functional pins 4.1.1 Power-down function Pin PWRDN (23) is used to power down the STA333W. PWRDN = 0 (0 V): power-down state. PWRND = 1 (V ): normal operation. During the power-down sequence the output begins to mute. After the mute condition is reached the power stage is switched off and the output becomes high impedance.

  • Page 17: Serial Audio Interface Description

    STA333W Functional description Serial audio interface description 4.2.1 Serial audio interface protocols The STA333W serial audio input was designed to interface with standard digital audio components and to accept serial data formats. The STA333W always acts as a slave when receiving audio input from standard digital audio components.

  • Page 18: I 2 C Bus Specification

    C bus specification STA333W C bus specification The STA333W supports the I C protocol via the input ports SCL and SDA. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver.

  • Page 19: Write Operation

    STA333W C bus specification Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333W acknowledges this and then waits for the byte of internal address. After receiving the internal byte address the STA333W again responds with an acknowledgement.

  • Page 20: Random Address Multi-Byte Read

    C bus specification STA333W 5.4.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer. Figure 10.

  • Page 21: Register Description

    STA333W Register description Register description Table 8. Register summary Addr Name 0x00 CONFA FDRB TWAB TWRB MCS2 MCS1 MCS0 0x01 CONFB C2IM C1IM Reserved SAIFB SAI3 SAI2 SAI1 SAI0 0x02 CONFC OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 0x03 CONFD Reserved Reserved 0x04 CONFE...

  • Page 22: Configuration Registers (Addr 0X00 To 0X05)

    Register description STA333W Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00) FDRB TWAB TWRB MCS2 MCS1 MCS0 Master clock select Table 9. Master clock select Name Description MCS0 Master clock select: Selects the ratio between the MCS1 input I S sample frequency and the input clock.

  • Page 23: Table 11. Interpolation Ratio Select

    STA333W Register description Interpolation ratio select Table 11. Interpolation ratio select Name Description Interpolation ratio select: Selects internal IR [1:0] interpolation ratio based on input I S sample frequency. The STA333W has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample.

  • Page 24: Configuration Register B (Addr 0X01)

    Register description STA333W Thermal warning adjustment bypass Table 14. Thermal warning adjustment Name Description Thermal warning adjustment bypass: TWAB 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block.

  • Page 25: Table 16. Serial Audio Input Interface Format

    STA333W Register description Serial audio input interface format Table 16. Serial audio input interface format Name Description SAI0 SAI1 Determines the interface format of the input serial digital audio interface. SAI2 SAI3 Serial data interface The STA333W audio serial input interfaces with standard digital audio components and accepts a number of serial data formats.

  • Page 26: Table 19. Supported Serial Audio Input Formats For Lsb-First (Saifb = 1)

    Register description STA333W Table 18. Support serial audio input formats for MSB first (SAIFB = 0) (continued) 0000 S 16- to 24-bit data 0001 Left justified 16- to 24-bit data 0010 Right justified 24-bit data 64* f 0110 Right justified 20-bit data 1010 Right justified 18-bit data 1110...

  • Page 27: Configuration Register C (Addr 0X02)

    STA333W Register description Channel input mapping Table 20. Channel input mapping Name Description 0: processing channel 1 receives left I S input C1IM 1: processing channel 1 receives right I S input 0: processing channel 2 receives left I S input C2IM 1: processing channel 2 receives right I S input...

  • Page 28: Configuration Register D (Addr 0X03)

    Register description STA333W Overcurrent warning detect adjustment bypass Table 23. Overcurrent warning detect adjustment bypass Name Description 0: overcurrent warning adjustment enabled OCRB 1: overcurrent warning adjustment disabled The status bit OCWARN is used to warn of an overcurrent condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default -3dB) in an attempt to eliminate the overcurrent warning condition.

  • Page 29: Table 26. Max Power Correction

    STA333W Register description Max power correction Table 26. Max power correction Name Description 1: enable power bridge correction for THD reduction near maximum power output. Setting the MPC bit turns on special processing that corrects the STA333W power device at high power.

  • Page 30: Configuration Register F (Addr 0X05)

    Register description STA333W Zero-crossing volume enable Table 31. Zero-crossing volume enable Name Description 1: volume adjustments will only occur at digital zero-crossings 0: volume adjustments will occur immediately The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible.

  • Page 31: Table 35. Lrck Double Trigger Protection

    STA333W Register description LRCK double trigger protection Table 35. LRCK double trigger protection Name Description LDTE LRCLK double trigger protection enable Actively prevents double trigger of LRCLK. Auto EAPD on clock loss Table 36. Auto EAPD on clock loss Name Description ECLE Auto EAPD on clock loss...

  • Page 32: Volume Control Registers (Addr 0X06 To 0X09)

    Register description STA333W Volume control registers (addr 0x06 to 0x09) 6.2.1 Mute/line output configuration register (addr 0x06) Reserved MMUTE Master mute Table 39. Master mute Name Description 0: normal operation MMUTE 1: all channels are in mute condition Channel mute Table 40.

  • Page 33: Master Volume Register (Addr 0X07)

    STA333W Register description 6.2.2 Master volume register (addr 0x07) 6.2.3 Channel volume (addr 0x08, 0x09) C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 Volume setting The volume structure of the STA333W consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting.

  • Page 34: Automodes™ Register (0X0C)

    Register description STA333W Table 42. Channel volume as a function of CxV CxV[7:0] Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB … … 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB …...

  • Page 35: Channel Configuration Registers (Addr 0X0E, 0X0F)

    STA333W Register description Table 44. Automodes™ AM switching frequency selection 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz 1.601 MHz - 1.700 MHz...

  • Page 36: Variable Distortion Compensation Registers (Addr 0X29, 0X2A)

    Register description STA333W Variable distortion compensation registers (addr 0x29, 0x2A) DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. Fault detect recovery constant registers (addr 0x2B, 0x2C) FDRC15 FDRC14...

  • Page 37: Reserved Registers (Addr 0X2E, 0X2F, 0X30, 0X31)

    STA333W Register description Table 45. Status bits description (continued) Name Description Overcurrent warning: OCWARN 0: warning 1: normal operation Overcurrent fault: OCFAULT 0: fault detected 1: normal operation Reserved Undervoltage warning: UVFAULT 0: VCCx below lower voltage threshold 1: normal operation Power bridge fault: FAULT 0: fault detected...

  • Page 38: Output Limit Register (Addr 0X34)

    Register description STA333W 6.11 Output limit register (addr 0x34) 6.11.1 Thermal and overcurrent warning output limit register OLIM7 OLIM6 OLIM5 OLIM4 OLIM3 OLIM2 OLIM1 OLIM0 The STA333W provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. When the TWARN or OCWARN status bit is asserted, the output is limited to the OLIM setting.

  • Page 39: Applications Information

    STA333W Applications information Applications information Applications scheme for power supplies Figure 11 below shows a typical applications scheme for STA333W. Special care has to be taken with regard to the power supplies when laying out the PCB. In particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device.

  • Page 40: Typical Output Configuration

    Applications information STA333W Figure 12. PLL filter circuit F IL T E R _ P L L F IL T E R _ P L L F IL T E R _ P L L F IL T E R _ P L L 2 K 2 2 K 2 2 K 2...

  • Page 41: Characterization Data

    STA333W Characterization data Characterization data = 8 Ω and f = 1 kHz unless otherwise The following characterizations were made with R stated. Figure 14. Output power vs. supply voltage (THD = 1%)  RKP 6 Ω  RKP 4 Ω 8 Ω...

  • Page 42: Figure 16. Fft -60 Dbfs (Vcc = 12 V)

    Characterization data STA333W Figure 16. FFT -60 dBfs (V = 12 V) -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 Figure 17. THD vs. frequency (V = 12 V, Po = 1 W) 4 Ω 4ohm 6 Ω...

  • Page 43: Figure 18. Fft 0 Dbfs (Vcc = 18 V)

    STA333W Characterization data Figure 18. FFT 0 dBfs (V = 18 V) -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 Figure 19. FFT -60 dBfs (V = 18 V) -100 -100 -110 -110 -120 -120 -130 -130 -140 -140...

  • Page 44: Package Thermal Characteristics

    Package thermal characteristics STA333W Package thermal characteristics A thermal resistance of 25 °C/W can be achieved by mounting the device on a PCB which has two copper ground areas of 3 x 3 cm and 16 vias (see Figure 21). Given that the amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level the maximum estimated dissipated power for the STA333W is 3 W.

  • Page 45: Figure 23. Powersso-36 Epd Outline Drawing

    STA333W Package mechanical data Package mechanical data The STA333W comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 23 below shows the package outline and Table 47 gives the dimensions. Figure 23. PowerSSO-36 EPD outline drawing Doc ID 13365 Rev 2 45/49...
  • Page 46 0.185 4.90 7.10 0.193 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.
  • Page 47 STA333W Trademarks and other acknowledgements Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automodes is a trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Sound Terminal is a trademark of STMicroelectronics. Doc ID 13365 Rev 2 47/49...

  • Page 48: Table 47. Table

    Revision history STA333W Revision history Table 48. Document revision history Date Revision Changes 25-May-2007 Initial release. Updated features for operating voltage range, digital gain increments and maximum power control on page 1 Updated description on page 1 Updated electrical specifications Table Table 3 Table 5 on...
  • Page 49 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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