Summary Of Device Errata - ST STM32L011 3 Series Errata Sheet

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Summary of device errata

The following table gives a quick reference to the STM32L011xx/L021xx device limitations and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
"-" = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Function
System
DMA
ADC
COMP
TIM
LPTIM
IWDG
RTC and TAMP
I2C
ES0332 - Rev 5
Table 3. Summary of device limitations
Section
2.1.1 Delay after an RCC peripheral clock enabling
2.1.2 I2C and USART cannot wake up the device from Stop mode
2.1.3 LDM, STM, PUSH and POP not allowed in IOPORT bus
2.1.4 BOOT_MODE bits do not reflect the selected boot mode
NSS pin synchronization required when using bootloader with SPI1
2.1.5
interface on TSSOP14 package
DMA disable failure and error flag omission upon simultaneous transfer
2.2.1
error and global flag clear
2.3.1 Overrun flag is not set if EOC reset coincides with new conversion end
Writing ADC_CFGR1 register while ADEN bit is set resets RES[1:0]
2.3.2
bitfield
2.3.3 Out-of-threshold value is not detected in AWD1 Single mode
COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit in
2.4.1
RCC_APB2RSTR register
PWM re-enabled in automatic output enable mode despite of system
2.5.1
break
2.5.3 Consecutive compare event missed in specific conditions
2.5.4 Output compare clear not working with external counter reset
2.6.1 Device may remain stuck in LPTIM interrupt when entering Stop mode
2.6.2 Device may remain stuck in LPTIM interrupt when clearing event flag
2.6.3 LPTIM events and PWM output are delayed by 1 kernel clock cycle
2.7.1 IWDG does not always reset the device
2.8.1 RTC calendar registers are not locked properly
2.8.2 RTC interrupt can be masked by another RTC interrupt
2.8.3 Calendar initialization may fail in case of consecutive INIT mode entry
2.8.4 Alarm flag may be repeatedly set when the core is stopped in debug
Detection of a tamper event occurring before enabling the tamper
2.8.5
detection is not supported in edge detection mode
10-bit master mode: new transfer cannot be launched if first part of the
2.9.1
address is not acknowledged by the slave
Wrong data sampling when data setup time (tSU;DAT) is shorter than one
2.9.3
I2C kernel clock period
STM32L011x3/4 STM32L021x3/4
Limitation
Summary of device errata
Status
Rev. Rev.
A 1, Z
A A
N -
N -
N N
A A
A A
P P
A A
A A
N N
P P
N N
P P
A A
P P
P P
N -
A A
A A
A A
N N
A A
A A
P P
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