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RM0461
5.5.7
PWR status clear register (PWR_SCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x018
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 CWRFBUSYF: Clear wakeup radio busy flag
Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 CWPVDF: Clear wakeup PVD interrupt flag
Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 CWUF3: Clear wakeup flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0.
Bit 1 CWUF2: Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0.
Bit 0 CWUF1: Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
w
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
w
RM0461 Rev 5
Power control (PWR)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
w
17
16
Res.
Res.
1
0
w
w
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