Power Status Register 2 (Pwr_Sr2) - STMicroelectronics STM32WLEx Reference Manual

RM0461
5.5.6

Power status register 2 (PWR_SR2)

This register is partially reset when exiting Standby/Shutdown modes.
Address offset: 0x014
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. PVMO3 Res. Res.
r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 PVMO3: Peripheral voltage monitoring output: V
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 PVDO: Programmable voltage detector output
Bit 10 VOSF: Voltage scaling flag
Bit 9 REGLPF: low-power regulator flag
Bit 8 REGLPS: low-power regulator started (ready)
28 27 26 25
Res. Res. Res.
12 11 10 9
PVDO VOSF
r r r
0: V voltage above PVM3 threshold (around 1.62 V)
DDA
1: V voltage below PVM3 threshold (around 1.62 V)
DDA
PVM3 output is valid after the PVM3 wakeup time.
0: V or voltage level on PVD_IN above the selected PVD threshold
DD
1: V or voltage level on PVD_IN below the selected PVD threshold
DD
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR control register 1
0: regulator ready in the selected voltage range
1: regulator output voltage changed to the required voltage level
This bit is set by hardware when the MCU is in LPRun mode. When the MCU exits from the
LPRun mode, this bit remains at 1 until the main regulator is ready. A polling on this bit must
be done before increasing the product frequency.
This bit is cleared by hardware when the main regulator is ready.
0: main regulator (MR) ready and used
1: low-power regulator (LPR) used
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still
cleared ("backup" SRAM2 disabled), the wakeup time from Standby mode may be
increased.
0: LPR not ready
1: LPR ready
24 23 22
Res. Res. Res.
8 7 6
r r r
DDA
(PWR_CR1).
RM0461 Rev 5
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
versus 1.62 V
17 16
Res. Res.
1 0
Res.
r
219/1306
229