Flash Wrp Area A Address Register (Flash_Wrp1Ar); Flash Wrp Area B Address Register (Flash_Wrp1Br) - STMicroelectronics STM32WLEx Reference Manual

Embedded flash memory (FLASH)
3.8.10

FLASH WRP area A address register (FLASH_WRP1AR)

Address offset: 0x02C
Reset value: 0xFF80 FFFF
Default reset value from ST production is given as.0b1111 1111 1XXX XXXX 1111 1111
1XXX XXXX, the option bits are loaded with user values from the flash memory at reset
release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP1A_END[6:0]: WRP area A end offset
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_STRT[6:0]: WRP area A start offset
3.8.11

FLASH WRP area B address register (FLASH_WRP1BR)

Address offset: 0x030
Reset value: 0xFF80 FFFF
Default reset value from ST production is given as 0b1111 1111 1XXX XXXX 1111 1111
1XXX XXXX, the option bits are loaded with user values from flash memory at reset release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU in RDP level 0 or RDP level 1.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
104/1306
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
Contains the last 2-Kbyte page of the WRP area A.
Contains the first 2-Kbyte page of the WRP area A.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
RM0461 Rev 5
21 20 19 18
WRP1A_END[6:0]
rw rw rw rw
5 4 3 2
WRP1A_STRT[6:0]
rw rw rw rw
21 20 19 18
WRP1B_END[6:0]
rw rw rw rw
5 4 3 2
WRP1B_STRT[6:0]
rw rw rw rw
RM0461
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw