How To Program The Watchdog Timeout; Figure 200. Window Watchdog Timing Diagram - ST STM32F40 Series Reference Manual

Window watchdog (WWDG)
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
19.4

How to program the watchdog timeout

You can use the formula in
Warning:

Figure 200. Window watchdog timing diagram

The formula to calculate the timeout value is given by:
where:
t
WWDG
t
PCLK1
Refer to the table below for the minimum and maximum values of the T
543/1422
Figure 200
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
T[6:0] CNT downcounter
W[6:0]
0x3F
Refresh not allowed
T6 bit
RESET
t t
=
WWDG PCLK1
: WWDG timeout
: APB1 clock period measured in ms
Doc ID 018909 Rev 4
to calculate the WWDG timeout.
Refresh allowed
WDGTB
× × ×
4096 2
Time
( [ ] ) ( )
t
5:0 + 1 ms
WWDG.
RM0090
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