Table of Contents
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RM0090
31
30
29
28
27
CTCIF7 CHTIF7 CTEIF7 CDMEIF7
Reserved
w
15
14
13
12
11
CTCIF5 CHTIF5 CTEIF5 CDMEIF5
Reserved
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register
26
25
24
Reserved
w
w
w
10
9
8
Reserved
w
w
w
Doc ID 018909 Rev 4
23
22
21
CFEIF7
CTCIF6
CHTIF6
w
w
7
6
5
CFEIF5
CTCIF4
CHTIF4
w
w
DMA controller (DMA)
20
19
18
CTEIF6 CDMEIF6
Reserved
w
w
w
4
3
2
CTEIF4 CDMEIF4
Reserved
w
w
w
17
16
CFEIF6
w
1
0
CFEIF4
w
238/1422
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