Rtc Shift Control Register (Rtc_Shiftr) - ST STM32F40 Series Reference Manual

RM0090
23.6.12

RTC shift control register (RTC_SHIFTR)

Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
ADD1S
w r r
15 14 13
Res.
r w w
Bit 31 ADD1S: Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
Bits 31:15 Reserved
Bits 14:0 SUBFS: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler's counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
Refer to
Note: This register is write protected. The write access procedure is described in
write protection on page 630
28 27 26 25
r r r r
12 11 10 9
w w w w
Delay (seconds) = SUBFS / ( PREDIV_S + 1 )
Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .
sure that the shadow registers have been updated with the shifted time.
Section 23.3.8: RTC
Doc ID 018909 Rev 4
24 23 22 21
Reserved
r r r r
8 7 6 5
SUBFS[14:0]
w w w w
synchronization.
Real-time clock (RTC)
20 19 18 17
r r r r
4 3 2 1
w w w w
RTC register
16
r
0
w
654/1422