Usart Mode Configuration; Usart Registers; Status Register (Usart_Sr); Table 122. Usart Mode Configuration - ST STM32F40 Series Reference Manual

Hide thumbs Also See for STM32F40 Series:

Table of Contents

USART mode configuration

Asynchronous mode

Hardware flow control

Multibuffer communication (DMA)

Multiprocessor communication

Half-duplex (single-wire mode)

1. X = supported; NA = not applicable.

The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).

Address offset: 0x00

Reset value: 0x00C0 0000

Bits 31:10 Reserved, must be kept at reset value

Bit 9 CTS: CTS flag

Note: This bit is not available for UART4 & UART5.

Bit 8 LBD: LIN break detection flag

Note: An interrupt is generated when LBD=1 if LBDIE=1

Universal synchronous asynchronous receiver transmitter (USART)

Section 1.1 on page 47

This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared

by software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3

0: No change occurred on the nCTS status line

1: A change occurred on the nCTS status line

This bit is set by hardware when the LIN break is detected. It is cleared by software (by

writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.

0: LIN Break not detected

1: LIN break detected

Doc ID 018909 Rev 4

USART1 USART2 USART3 UART4

for a list of abbreviations used in register descriptions.

UART5 USART6

Do you have a question about the STM32F40 Series and is the answer not in the manual?