Spi And I 2 S Registers; Spi Control Register 1 (Spi_Cr1) (Not Used In I 2 S Mode) - ST STM32F40 Series Reference Manual

Serial peripheral interface (SPI)
27.5 SPI and I
Refer to
The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
27.5.1 SPI control register 1 (SPI_CR1) (not used in I
Address offset: 0x00
Reset value: 0x0000
15 14 13
BIDI BIDI CRC CRC
MODE OE EN NEXT
rw rw rw
Bit 15 BIDIMODE: Bidirectional data mode enable
Note: Not used in I
Bit 14 BIDIOE: Output enable in bidirectional mode
Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
Bit 13 CRCEN: Hardware CRC calculation enable
Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation
Bit 12 CRCNEXT: CRC transfer next
Note: When the SPI is configured in full duplex or transmitter only modes, CRCNEXT must be
Bit 11 DFF: Data frame format
Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation
837/1422
2
S registers
Section 1.1 on page 47
12 11 10 9
RX
DFF SSM
ONLY
rw rw rw rw
0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
2
S mode
This bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
2
Not used in I S mode
0: CRC calculation disabled
1: CRC calculation enabled
2
Not used in I S mode
0: Data phase (no CRC phase)
1: Next transfer is CRC (CRC phase)
written as soon as the last data is written to the SPI_DR register.
When the SPI is configured in receiver only mode, CRCNEXT must be set after the
second last data reception.
This bit should be kept cleared when the transfers are managed by DMA.
2
Not used in I S mode
0: 8-bit data frame format is selected for transmission/reception
1: 16-bit data frame format is selected for transmission/reception
2
Not used in I S mode
Doc ID 018909 Rev 4
for a list of abbreviations used in register descriptions.
8 7 6
LSB
SSI SPE
FIRST
rw rw rw
2
S mode)
5 4 3 2
BR [2:0] MSTR
rw rw rw rw
RM0090
1 0
CPOL CPHA
rw rw