Can Registers; Register Access Protection; Can Control And Status Registers; Figure 229. Transmit Mailbox States - ST STM32F40 Series Reference Manual

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The error and status change interrupt can be generated by the following events:

CAN registers

The peripheral registers have to be accessed by words (32 bits).

Erroneous access to certain configuration registers can cause the hardware to temporarily

disturb the whole CAN network. Therefore the CAN_BTR register can be modified by

software only while the CAN hardware is in initialization mode.

Although the transmission of incorrect data will not cause problems at the CAN network

level, it can severely disturb the application. A transmit mailbox can be only modified by

software while it is in empty state, refer to

The filter values can be modified either deactivating the associated filter banks or by setting

the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO

assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when

the filter initialization mode is set (FINIT=1) in the CAN_FMR register.

CAN master control register (CAN_MCR)

Address offset: 0x00

Reset value: 0x0001 0002

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 DBF: Debug freeze

0: CAN working during debug

1: CAN reception/transmission frozen during debug. Reception FIFOs can still be

accessed/controlled normally.

FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.

Error condition, for more details on error conditions please refer to the CAN Error

Status register (CAN_ESR).

Wakeup condition, SOF monitored on the CAN Rx signal.

Entry into Sleep mode.

for a list of abbreviations used in register descriptions.

Doc ID 018909 Rev 4

Figure 229: Transmit mailbox

Controller area network (bxCAN)

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