ST STM32F40 Series Reference Manual page 983

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MAC debug register (ETH_MACDBGR)
Address offset: 0x0034
Reset value: 0x0000 0000
This debug register gives the status of all the main modules of the transmit and receive data
paths and the FIFOs. An all-zero status indicates that the MAC core is in Idle state (and
FIFOs are empty) and no activity is going on in the data paths.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ro
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 TFF: Tx FIFO full
Bit 24 TFNE: Tx FIFO not empty
Bit 23 Reserved, must be kept at reset value.
Bit 22 TFWA: Tx FIFO write active
Bits 21:20 TFRS: Tx FIFO read status
Bit 19 MTP: MAC transmitter in pause
Bits 18:17 MTFCS: MAC transmit frame controller status
Bit 16 MMTEA: MAC MII transmit engine active
Bits 15:10 Reserved, must be kept at reset value.
983/1422
ro ro ro ro ro
When high, it indicates that the Tx FIFO is full and hence no more frames will be accepted
for transmission.
When high, it indicates that the TxFIFO is not empty and has some data left for
transmission.
When high, it indicates that the TxFIFO write controller is active and transferring data to the
TxFIFO.
This indicates the state of the TxFIFO read controller:
00: Idle state
01: Read state (transferring data to the MAC transmitter)
10: Waiting for TxStatus from MAC transmitter
11: Writing the received TxStatus or flushing the TxFIFO
When high, it indicates that the MAC transmitter is in Pause condition (in full-duplex mode
only) and hence will not schedule any frame for transmission
This indicates the state of the MAC transmit frame controller:
00: Idle
01: Waiting for Status of previous frame or IFG/backoff period to be over
10: Generating and transmitting a Pause control frame (in full duplex mode)
11: Transferring input frame for transmission
When high, it indicates that the MAC MII transmit engine is actively transmitting data and
that it is not in the Idle state.
Doc ID 018909 Rev 4
Reserved
ro ro ro
9 8 7 6 5 4 3
ro ro ro ro ro
RM0090
2 1 0
ro ro ro