Receiver; Figure 250. Start Bit Detection When Oversampling By 16 Or 8 - ST STM32F40 Series Reference Manual

RM0090
26.3.3

Receiver

The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.
Start bit detection
The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.

Figure 250. Start bit detection when oversampling by 16 or 8

Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set) where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NE noise
flag is set if, for both samplings, at least 2 out of the 3 sampled bits are at 0 (sampling on the
3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). If this condition is not met,
the start detection aborts and the receiver returns to the idle state (no flag is set).
If, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th
and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the NE noise
flag bit is set.
Universal synchronous asynchronous receiver transmitter (USART)
RX state
RX line
Ideal
sample
1
clock
Real
X
sample
clock
Conditions
1 1 1 0
to validate
the start bit
Falling edge
detection
Doc ID 018909 Rev 4
Idle
2 3 4 5 6 7 8
sampled values
X X X X X X X
7/16
One-bit time
X 0 X 0 X 0 0 0
At least 2 bits At least 2 bits
out of 3 at 0 out of 3 at 0
Start bit
9 10 11 12 13 14 15 16
9 10 11 12 13 14 15 16
6/16
7/16
0 X X X X X X
ai15471
750/1422