I 2 C Data Register (I2C_Dr); I 2 C Status Register 1 (I2C_Sr1) - ST STM32F40 Series Reference Manual

Inter-integrated circuit (I
2
25.6.5 I C Data register (I2C_DR)
Address offset: 0x10
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:8 Reserved, must be kept at reset value
Bits 7:0 DR[7:0] 8-bit data register
Note: In slave mode, the address is not copied into DR.
Note: Write collision is not managed (DR can be written if TxE=0).
Note: If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so
2
25.6.6 I C Status register 1 (I2C_SR1)
Address offset: 0x14
Reset value: 0x0000
15 14 13 12
SMB TIME PEC
ALERT OUT ERR
Res.
rc_w0 rc_w0 rc_w0
Bit 15 SMBALERT: SMBus alert
– Cleared by software writing 0, or by hardware when PE=0.
Bit 14 TIMEOUT: Timeout or Tlow error
– When set in slave mode: slave resets the communication and lines are released by hardware
– When set in master mode: Stop condition sent by hardware
– Cleared by software writing 0, or by hardware when PE=0.
Note: This functionality is available only in SMBus mode.
733/1422
2
C) interface
11 10 9
Byte received or to be transmitted to the bus.
–Transmitter mode: Byte transmission starts automatically when a byte is written in the DR
register. A continuous transmit stream can be maintained if the next data to be transmitted
is put in DR once the transmission is started (TxE=1)
–Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream
can be maintained if DR is read before the next data byte is received (RxNE=1).
cannot be read.
11 10 9
OVR AF ARLO
rc_w0 rc_w0 rc_w0
In SMBus host mode:
0: no SMBALERT
1: SMBALERT event occurred on pin
In SMBus slave mode:
0: no SMBALERT response address header
1: SMBALERT response address header to SMBALERT LOW received
0: No timeout error
1: SCL remained LOW for 25 ms (Timeout)
or
Master cumulative clock low extend time more than 10 ms (Tlow:mext)
or
Slave cumulative clock low extend time more than 25 ms (Tlow:sext)
Doc ID 018909 Rev 4
8 7 6
rw rw rw
8 7 6
BERR TxE RxNE
Res.
rc_w0 r r
5 4 3 2
DR[7:0]
rw rw rw
5 4 3 2
STOPF ADD10 BTF
r r r
RM0090
1 0
rw rw
1 0
ADDR SB
r r