Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr) - ST STM32F40 Series Reference Manual

RM0090
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode
Bit 6 RNGLPEN: Random number generator clock enable during Sleep mode
Bit 5 HASHLPEN: Hash modules clock enable during Sleep mode
Bit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode
Bit 3:1 Reserved, must be kept at reset value.
Bit 0 DCMILPEN: Camera interface enable during Sleep mode
6.3.22 RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR)
Address offset: 0x58
Reset value: 0x0000 0001
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:1Reserved, must be kept at reset value.
FSMCLPEN: Flexible static memory controller module clock enable during Sleep mode
Set and cleared by software.
Bit 0
0: FSMC module clock disabled during Sleep mode
1: FSMC module clock enabled during Sleep mode
Set and cleared by software.
0: USB OTG FS clock disabled during Sleep mode
1: USB OTG FS clock enabled during Sleep mode
Set and cleared by software.
0: Random number generator clock disabled during Sleep mode
1: Random number generator clock enabled during Sleep mode
Set and cleared by software.
0: Hash modules clock disabled during Sleep mode
1: Hash modules clock enabled during Sleep mode
Set and cleared by software.
0: cryptography modules clock disabled during Sleep mode
1: cryptography modules clock enabled during Sleep mode
Set and cleared by software.
0: Camera interface clock disabled during Sleep mode
1: Camera interface clock enabled during Sleep mode
28 27 26 25
12 11 10 9
Doc ID 018909 Rev 4
24 23 22
Reserved
8 7 6
Reserved
Reset and clock control for (RCC)
21 20 19 18
5 4 3 2
17 16
1 0
FSMC
LPEN
rw
164/1422