Conversions Without Dma And Without Overrun Detection; Multi Adc Mode - ST STM32F40 Series Reference Manual

Analog-to-digital converter (ADC)
11.8.3

Conversions without DMA and without overrun detection

It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). For that, the DMA must be disabled
(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this
configuration, overrun detection is disabled.
11.9

Multi ADC mode

In devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs)
ADC modes can be used (see
In multi ADC mode, the start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the
MULTI[4:0] bits in the ADC_CCR register.
Note: In multi ADC mode, when configuring conversion trigger by an external event, the
application must set trigger by the master only and disable trigger by slaves to prevent
spurious triggers that would start unwanted slave conversions.
The four possible modes below are implemented:
●
Injected simultaneous mode
● Regular simultaneous mode
●
Interleaved mode
● Alternate trigger mode
It is also possible to use the previous modes combined in the following ways:
●
Injected simultaneous mode + Regular simultaneous mode
●
Regular simultaneous mode + Alternate trigger mode
Note: In multi ADC mode, the converted data can be read on the multi-mode data register
(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).
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Figure 41).
Doc ID 018909 Rev 4
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