Rtc Time Stamp Date Register (Rtc_Tsdr); Rtc Timestamp Sub Second Register (Rtc_Tsssr) - ST STM32F40 Series Reference Manual

RM0090
23.6.14

RTC time stamp date register (RTC_TSDR)

Address offset: 0x34
Power-on reset value: 0x0000 0000
System reset: not affected
31 30 29
15 14 13
WDU[1:0]
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 WDU[1:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bit 3:0 DU[3:0]: Date units in BCD format
Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
23.6.15

RTC timestamp sub second register (RTC_TSSSR)

Address offset: 0x38
Power-on reset value: 0x0000 0000
System reset: not affected
31 30 29
r r r
15 14 13
r r r
Bits 31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler's counter when the timestamp event
occurred.
Note: The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
28 27 26 25
12 11 10 9
MT MU[3:0]
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
Doc ID 018909 Rev 4
24 23 22 21
Reserved
8 7 6 5
DT[1:0]
Reserved
r r
24 23 22 21
Reserved
r r r r
8 7 6 5
SS[15:0]
r r r r
Real-time clock (RTC)
20 19 18 17
4 3 2 1
DU[3:0]
r r r r
20 19 18 17
r r r r
4 3 2 1
r r r r
16
0
r
16
r
0
r
656/1422