Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr) - ST STM32F40 Series Reference Manual

Reset and clock control for (RCC)
6.3.12

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0010 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
ETHMA
OTGHS OTGHS
CPTPE
Reser-
ULPIEN EN
N
ved
rw rw rw
15 14 13 12
CRCEN
Reserved
rw
Bits 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable
Set and cleared by software.
0: USB OTG HS ULPI clock disabled
1: USB OTG HS ULPI clock enabled
Bit 29 OTGHSEN: USB OTG HS clock enable
Set and cleared by software.
0: USB OTG HS clock disabled
1: USB OTG HS clock enabled
Bit 28 ETHMACPTPEN: Ethernet PTP clock enable
Set and cleared by software.
0: Ethernet PTP clock disabled
1: Ethernet PTP clock enabled
Bit 27 ETHMACRXEN: Ethernet Reception clock enable
Set and cleared by software.
0: Ethernet Reception clock disabled
1: Ethernet Reception clock enabled
Bit 26 ETHMACTXEN: Ethernet Transmission clock enable
Set and cleared by software.
0: Ethernet Transmission clock disabled
1: Ethernet Transmission clock enabled
Bit 25 ETHMACEN: Ethernet MAC clock enable
Set and cleared by software.
0: Ethernet MAC clock disabled
1: Ethernet MAC clock enabled
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
145/1422
27 26 25
ETHMA ETHMA ETHMA
CRXEN CTXEN CEN
rw rw rw
11 10 9
GPIOIE
Reserved
Doc ID 018909 Rev 4
24 23 22 21
DMA2EN DMA1EN
Reserved
rw rw
8 7 6 5
GPIOH GPIOGE GPIOFE
N EN N N
rw rw rw rw
20 19 18
CCMDATA BKPSR
Res.
RAMEN AMEN
rw
4 3 2
GPIOD GPIOC GPIOB
GPIOEEN
EN EN
rw rw rw
RM0090
17 16
Reserved
1 0
GPIOA
EN EN
rw rw