Dma Stream X Configuration Register (Dma_Sxcr) (X = 0 - ST STM32F40 Series Reference Manual

DMA controller (DMA)
9.5.5

DMA stream x configuration register (DMA_SxCR) (x = 0..7)

This register is used to configure the concerned stream.
Address offset: 0x10 + 0x18 × stream number
Reset value: 0x0000 0000
31 30 29
Reserved
15 14 13
PINCOS MSIZE[1:0]
rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:25 CHSEL[2:0]: Channel selection
These bits are set and cleared by software.
000: channel 0 selected
001: channel 1 selected
010: channel 2 selected
011: channel 3 selected
100: channel 4 selected
101: channel 5 selected
110: channel 6 selected
111: channel 7 selected
These bits are protected and can be written only if EN is '0'
Bits 24:23 MBURST: Memory burst transfer configuration
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is '0'
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.
Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is '0'
In direct mode, these bits are forced to 0x0 by hardware.
Bits 20 Reserved, must be kept at reset value.
Bits 19 CT: Current target (only in double buffer mode)
This bits is set and cleared by hardware. It can also be written by software.
0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)
1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)
This bit can be written only if EN is '0' to indicate the target memory area of the first transfer.
Once the stream is enabled, this bit operates as a status flag indicating which memory area
is the current target.
239/1422
28 27 26 25
CHSEL[3:0]
rw rw rw
12 11 10 9
PSIZE[1:0] MINC PINC
rw rw rw rw
Doc ID 018909 Rev 4
24 23 22 21
MBURST [1:0] PBURST[1:0]
rw rw rw rw
8 7 6 5
CIRC DIR[1:0] PFCTRL
rw rw rw rw
20 19 18
DBM or
CT
Reserv
reserved
ed
rw rw or r
4 3 2
TCIE HTIE TEIE DMEIE
rw rw rw
RM0090
17 16
PL[1:0]
rw rw
1 0
EN
rw rw