ST STM32F40 Series Reference Manual page 734

RM0090
Bit 13 Reserved, must be kept at reset value
Bit 12 PECERR: PEC Error in reception
Bit 11 OVR: Overrun/Underrun
Note: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a
Bit 10 AF: Acknowledge failure
Bit 9 ARLO: Arbitration lost (master mode)
Note: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase,
Bit 8 BERR: Bus error
Bit 7 TxE: Data register empty (transmitters)
Note: TxE is not cleared by writing the first data being transmitted, or by writing data when
0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: PEC error: receiver returns NACK after PEC reception (whatever ACK)
–Cleared by software writing 0, or by hardware when PE=0.
–Note: When the received CRC is wrong, PECERR is not set in slave mode if the PEC
control bit is not set before the end of the CRC reception. Nevertheless, reading the PEC
value determines whether the received CRC is right or wrong.
0: No overrun/underrun
1: Overrun or underrun
–Set by hardware in slave mode when NOSTRETCH=1 and:
–In reception when a new byte is received (including ACK pulse) and the DR register has not
been read yet. New received byte is lost.
–In transmission when a new byte should be sent and the DR register has not been written
yet. The same byte is sent twice.
–Cleared by software writing 0, or by hardware when PE=0.
hold timing error occurs
0: No acknowledge failure
1: Acknowledge failure
–Set by hardware when no acknowledge is returned.
–Cleared by software writing 0, or by hardware when PE=0.
0: No Arbitration Lost detected
1: Arbitration Lost detected
Set by hardware when the interface loses the arbitration of the bus to another master
–Cleared by software writing 0, or by hardware when PE=0.
After an ARLO event the interface switches back automatically to Slave mode (M/SL=0).
or the acknowledge transmission (not on the address acknowledge).
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
–Set by hardware when the interface detects an SDA rising or falling edge while SCL is high,
occurring in a non-valid position during a byte transfer.
–Cleared by software writing 0, or by hardware when PE=0.
0: Data register not empty
1: Data register empty
–Set when DR is empty in transmission. TxE is not set during address phase.
–Cleared by software writing to the DR register or by hardware after a start or a stop
condition or when PE=0.
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
BTF is set, as in both cases the data register is still empty.
Doc ID 018909 Rev 4
Inter-integrated circuit (I
2
C) interface
734/1422