I2C Register Map; Table 106. I2C Register Map And Reset Values - ST STM32F40 Series Reference Manual

Inter-integrated circuit (I
2
25.6.11 I C register map
The table below provides the I
2
Table 106. I C register map and reset values
Offset Register
I2C_CR1
0x00
Reset value
I2C_CR2
0x04
Reset value
I2C_OAR1
0x08
Reset value
I2C_OAR2
0x0C
Reset value
I2C_DR
0x10
Reset value
I2C_SR1
0x14
Reset value
I2C_SR2
0x18
Reset value
I2C_CCR
0x1C
Reset value
I2C_TRISE
0x20
Reset value
I2C_FLTR
0x24
Reset value
Refer to
741/1422
2
C) interface
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2 on page 52 for the register boundary addresses table.
Doc ID 018909 Rev 4
2
C register map and reset values.
0
Reserved
0
Reserved
Reserved
0 0
0 0
0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0
ADD[9:8]
0 0 0 0
0 0
0 0
0 0 0 0 0 0 0
PEC[7:0]
0 0 0 0 0 0 0 0
CCR[11:0]
0 0 0 0 0 0
RM0090
0 0 0 0 0
FREQ[5:0]
0 0 0 0 0 0
ADD[7:1]
0 0 0 0 0 0
ADD2[7:1]
0 0 0 0 0 0
DR[7:0]
0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0
TRISE[5:0]
0 0 0 0 1 0
DNF[3:0]
0 0 0 0 0