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Universal synchronous asynchronous receiver transmitter (USART)
Character reception
During an USART reception, data shifts in least significant bit first through the RX pin. In this
mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the
received shift register.
Procedure:
1.
Enable the USART by writing the UE bit in USART_CR1 register to 1.
2.
Program the M bit in USART_CR1 to define the word length.
3.
Program the number of stop bits in USART_CR2.
4.
Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication. STEP 3
5.
Select the desired baud rate using the baud rate register USART_BRR
6.
Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received
●
The RXNE bit is set. It indicates that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
●
An interrupt is generated if the RXNEIE bit is set.
●
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
●
In multibuffer, RXNE is set after every byte received and is cleared by the DMA read to
the Data Register.
●
In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The
RXNE bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Note:
The RE bit should not be reset while receiving data. If the RE bit is disabled during
reception, the reception of the current byte will be aborted.
Break character
When a break character is received, the USART handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the IDLEIE bit is set.
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
●
The ORE bit is set.
751/1422
Doc ID 018909 Rev 4
RM0090
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