Spi And I 2 S Main Features; Spi Features - ST STM32F40 Series Reference Manual

Serial peripheral interface (SPI)
27.2 SPI and I
27.2.1

SPI features

●
Full-duplex synchronous transfers on three lines
●
Simplex synchronous transfers on two lines with or without a bidirectional data line
●
8- or 16-bit transfer frame format selection
●
Master or slave operation
●
Multimaster mode capability
●
8 master mode baud rate prescalers (f
● Slave mode frequency (f
●
Faster communication for both master and slave
● NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
●
Programmable clock polarity and phase
●
Programmable data order with MSB-first or LSB-first shifting
●
Dedicated transmission and reception flags with interrupt capability
●
SPI bus busy status flag
●
SPI TI mode
●
Hardware CRC feature for reliable communication:
–
–
●
Master mode fault, overrun and CRC error flags with interrupt capability
●
1-byte transmission and reception buffer with DMA capability: Tx and Rx requests
795/1422
2
S main features
PCLK
CRC value can be transmitted as last byte in Tx mode
Automatic CRC error checking for last received byte
Doc ID 018909 Rev 4
/2 max.)
PCLK
/2 max)
RM0090