I 2 C Control Register 2 (I2C_Cr2) - ST STM32F40 Series Reference Manual

RM0090
Bit 3 SMBTYPE: SMBus type
Bit 2 Reserved, must be kept at reset value
Bit 1 SMBUS: SMBus mode
Bit 0 PE: Peripheral enable
Note: If this bit is reset while a communication is on going, the peripheral is disabled at the
Note: When the STOP, START or PEC bit is set, the software must not perform any write access to
I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a second
STOP, START or PEC request.
2
25.6.2 I C Control register 2 (I2C_CR2)
Address offset: 0x04
Reset value: 0x0000
15 14 13
LAST
Reserved
Bits 15:13 Reserved, must be kept at reset value
Bit 12 LAST: DMA last transfer
Note: This bit is used in master receiver mode to permit the generation of a NACK on the last
Bit 11 DMAEN: DMA requests enable
Bit 10 ITBUFEN: Buffer interrupt enable
0: SMBus Device
1: SMBus Host
2
0: I C mode
1: SMBus mode
0: Peripheral disable
1: Peripheral enable
end of the current communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.
In master mode, this bit must not be reset before the end of the communication.
12 11 10 9
DMA ITBUF ITEVT
EN EN EN
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0: Next DMA EOT is not the last transfer
1: Next DMA EOT is the last transfer
received data.
0: DMA requests disabled
1: DMA request enabled when TxE=1 or RxNE =1
0: TxE = 1 or RxNE = 1 does not generate any interrupt.
1:TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)
Doc ID 018909 Rev 4
Inter-integrated circuit (I
8 7 6
ITERR
EN
Reserved
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5 4 3 2
FREQ[5:0]
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2
C) interface
1 0
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