Figure 211. Aes-Ctr Mode Encryption - ST STM32F40 Series Reference Manual

Cryptographic processor (CRYP)
Figure 211

Figure 211. AES-CTR mode encryption

1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or
after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when
encoding); P: plain text; IV: Initialization vectors.
561/1422
and Figure 212 illustrate AES-CTR encryption and decryption, respectively.
AHB2 data write
(before CRYP
is enabled)
+1
K0...3
(I + 1) is written
back into IV
at same time
than C is pushed
in OUT FIFO
Doc ID 018909 Rev 4
IN FIFO
plaintext P
DATATYPE
swapping
IV0...1(L/R)
I, 128 bits
128, 192
or 256
AEA, encrypt
O, 128 bits
+
DATATYPE
swapping
OUT FIFO
ciphertext C
P, 128 bits
Ps, 128 bits
Cs, 128 bit
C, 128 bits
RM0090
ai16073b