Pwr Register Map; Table 24. Pwr - Register Map And Reset Values For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx - ST STM32F40 Series Reference Manual

Power controller (PWR)
Bit 8 EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 BRR: Backup regulator ready
Set by hardware to indicate that the Backup Regulator is ready.
0: Backup Regulator not ready
1: Backup Regulator ready
Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
1: V
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR_CR register.
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CWUF bit in the PWR_CR register.
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
5.5

PWR register map

The following table summarizes the PWR registers.
Table 24. PWR - register map and reset values for STM32F405xx/07xx and STM32F415xx/17xx
Offset Register
PWR_CR
0x000
Reset value
PWR_CSR
0x004
Reset value
109/1422
or power reset.
is higher than the PVD threshold selected with the PLS[2:0] bits.
DD
is lower than the PVD threshold selected with the PLS[2:0] bits.
DD
Standby or reset until the PVDE bit is set.
EWUP bit) when the WKUP pin level is already high.
Reserved
Reserved
Doc ID 018909 Rev 4
PLS[2:0]
Reserved
1 0 0 0 0
Reserved Reserved
0 0 0
RM0090
0 0 0 0 0 0
0 0 0 0