Glossary; Peripheral Availability - ST STM32F40 Series Reference Manual

RM0090
1.2

Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:
●
The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this
document
●
The CPU core integrates two debug ports:
–
–
●
Word: data/instruction of 32-bit length.
●
Half word: data/instruction of 16-bit length.
● Byte: data of 8-bit length.
●
Double word: data of 64-bit length.
● IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a
microcontroller while the user program is running.
●
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
●
I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction
interface. Prefetch is performed on this bus.
●
D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU
to the Flash data interface.
● Option bytes: product configuration bits stored in the Flash memory.
●
OBL: option byte loader.
● AHB: advanced high-performance bus.
●
CPU: refers to the Cortex-M4F core.
1.3

Peripheral availability

For peripheral availability and number across all STM32F405xx/07xx and
STM32F415xx/17xx sales types, please refer to the STM32F405xx/07xx and
STM32F415xx/17xx datasheets.
For peripheral availability and number across all STM32F42xxx and STM32F43xxx sales
types, please refer to the STM32F42xxx and STM32F43xxx datasheets.
JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, please refer to the Cortex-M4F Technical
Reference Manual
Doc ID 018909 Rev 4
Documentation conventions
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